183d290c5STom Rini // SPDX-License-Identifier: GPL-2.0+ 2214ffae0SHongbo Zhang /* 3214ffae0SHongbo Zhang * Copyright 2016 Freescale Semiconductor, Inc. 4214ffae0SHongbo Zhang * Author: Hongbo Zhang <hongbo.zhang@nxp.com> 5214ffae0SHongbo Zhang * This file implements LS102X platform PSCI SYSTEM-SUSPEND function 6214ffae0SHongbo Zhang */ 7214ffae0SHongbo Zhang 8214ffae0SHongbo Zhang #include <config.h> 9214ffae0SHongbo Zhang #include <asm/io.h> 10214ffae0SHongbo Zhang #include <asm/psci.h> 11214ffae0SHongbo Zhang #include <asm/arch/immap_ls102xa.h> 12214ffae0SHongbo Zhang #include <fsl_immap.h> 13214ffae0SHongbo Zhang #include "fsl_epu.h" 14214ffae0SHongbo Zhang 15214ffae0SHongbo Zhang #define __secure __attribute__((section("._secure.text"))) 16214ffae0SHongbo Zhang 17214ffae0SHongbo Zhang #define CCSR_GICD_CTLR 0x1000 18214ffae0SHongbo Zhang #define CCSR_GICC_CTLR 0x2000 19214ffae0SHongbo Zhang #define DCSR_RCPM_CG1CR0 0x31c 20214ffae0SHongbo Zhang #define DCSR_RCPM_CSTTACR0 0xb00 21214ffae0SHongbo Zhang #define DCFG_CRSTSR_WDRFR 0x8 22214ffae0SHongbo Zhang #define DDR_RESV_LEN 128 23214ffae0SHongbo Zhang 24214ffae0SHongbo Zhang #ifdef CONFIG_LS1_DEEP_SLEEP 25214ffae0SHongbo Zhang /* 26214ffae0SHongbo Zhang * DDR controller initialization training breaks the first 128 bytes of DDR, 27214ffae0SHongbo Zhang * save them so that the bootloader can restore them while resuming. 28214ffae0SHongbo Zhang */ 29214ffae0SHongbo Zhang static void __secure ls1_save_ddr_head(void) 30214ffae0SHongbo Zhang { 31214ffae0SHongbo Zhang const char *src = (const char *)CONFIG_SYS_SDRAM_BASE; 32214ffae0SHongbo Zhang char *dest = (char *)(OCRAM_BASE_S_ADDR + OCRAM_S_SIZE - DDR_RESV_LEN); 33214ffae0SHongbo Zhang struct ccsr_scfg __iomem *scfg = (void *)CONFIG_SYS_FSL_SCFG_ADDR; 34214ffae0SHongbo Zhang int i; 35214ffae0SHongbo Zhang 36214ffae0SHongbo Zhang out_le32(&scfg->sparecr[2], dest); 37214ffae0SHongbo Zhang 38214ffae0SHongbo Zhang for (i = 0; i < DDR_RESV_LEN; i++) 39214ffae0SHongbo Zhang *dest++ = *src++; 40214ffae0SHongbo Zhang } 41214ffae0SHongbo Zhang 42214ffae0SHongbo Zhang static void __secure ls1_fsm_setup(void) 43214ffae0SHongbo Zhang { 44214ffae0SHongbo Zhang void *dcsr_epu_base = (void *)(CONFIG_SYS_DCSRBAR + EPU_BLOCK_OFFSET); 45295a24b3SYork Sun void *dcsr_rcpm_base = (void *)SYS_FSL_DCSR_RCPM_ADDR; 46214ffae0SHongbo Zhang 47214ffae0SHongbo Zhang out_be32(dcsr_rcpm_base + DCSR_RCPM_CSTTACR0, 0x00001001); 48214ffae0SHongbo Zhang out_be32(dcsr_rcpm_base + DCSR_RCPM_CG1CR0, 0x00000001); 49214ffae0SHongbo Zhang 50214ffae0SHongbo Zhang fsl_epu_setup((void *)dcsr_epu_base); 51214ffae0SHongbo Zhang 52214ffae0SHongbo Zhang /* Pull MCKE signal low before enabling deep sleep signal in FPGA */ 53214ffae0SHongbo Zhang out_be32(dcsr_epu_base + EPECR0, 0x5); 54214ffae0SHongbo Zhang out_be32(dcsr_epu_base + EPSMCR15, 0x76300000); 55214ffae0SHongbo Zhang } 56214ffae0SHongbo Zhang 57214ffae0SHongbo Zhang static void __secure ls1_deepsleep_irq_cfg(void) 58214ffae0SHongbo Zhang { 59214ffae0SHongbo Zhang struct ccsr_scfg __iomem *scfg = (void *)CONFIG_SYS_FSL_SCFG_ADDR; 60214ffae0SHongbo Zhang struct ccsr_rcpm __iomem *rcpm = (void *)CONFIG_SYS_FSL_RCPM_ADDR; 61214ffae0SHongbo Zhang u32 ippdexpcr0, ippdexpcr1, pmcintecr = 0; 62214ffae0SHongbo Zhang 63214ffae0SHongbo Zhang /* Mask interrupts from GIC */ 64214ffae0SHongbo Zhang out_be32(&rcpm->nfiqoutr, 0x0ffffffff); 65214ffae0SHongbo Zhang out_be32(&rcpm->nirqoutr, 0x0ffffffff); 66214ffae0SHongbo Zhang /* Mask deep sleep wake-up interrupts while entering deep sleep */ 67214ffae0SHongbo Zhang out_be32(&rcpm->dsimskr, 0x0ffffffff); 68214ffae0SHongbo Zhang 69214ffae0SHongbo Zhang ippdexpcr0 = in_be32(&rcpm->ippdexpcr0); 70214ffae0SHongbo Zhang /* 71214ffae0SHongbo Zhang * Workaround: There is bug of register ippdexpcr1, when read it always 72214ffae0SHongbo Zhang * returns zero, so its value is saved to a scrachpad register to be 73214ffae0SHongbo Zhang * read, that is why we don't read it from register ippdexpcr1 itself. 74214ffae0SHongbo Zhang */ 75214ffae0SHongbo Zhang ippdexpcr1 = in_le32(&scfg->sparecr[7]); 76*26cbc0d6SRan Wang out_be32(&rcpm->ippdexpcr1, ippdexpcr1); 77214ffae0SHongbo Zhang 78214ffae0SHongbo Zhang if (ippdexpcr0 & RCPM_IPPDEXPCR0_ETSEC) 79214ffae0SHongbo Zhang pmcintecr |= SCFG_PMCINTECR_ETSECRXG0 | 80214ffae0SHongbo Zhang SCFG_PMCINTECR_ETSECRXG1 | 81214ffae0SHongbo Zhang SCFG_PMCINTECR_ETSECERRG0 | 82214ffae0SHongbo Zhang SCFG_PMCINTECR_ETSECERRG1; 83214ffae0SHongbo Zhang 84214ffae0SHongbo Zhang if (ippdexpcr0 & RCPM_IPPDEXPCR0_GPIO) 85214ffae0SHongbo Zhang pmcintecr |= SCFG_PMCINTECR_GPIO; 86214ffae0SHongbo Zhang 87214ffae0SHongbo Zhang if (ippdexpcr1 & RCPM_IPPDEXPCR1_LPUART) 88214ffae0SHongbo Zhang pmcintecr |= SCFG_PMCINTECR_LPUART; 89214ffae0SHongbo Zhang 90214ffae0SHongbo Zhang if (ippdexpcr1 & RCPM_IPPDEXPCR1_FLEXTIMER) 91214ffae0SHongbo Zhang pmcintecr |= SCFG_PMCINTECR_FTM; 92214ffae0SHongbo Zhang 93214ffae0SHongbo Zhang /* Always set external IRQ pins as wakeup source */ 94214ffae0SHongbo Zhang pmcintecr |= SCFG_PMCINTECR_IRQ0 | SCFG_PMCINTECR_IRQ1; 95214ffae0SHongbo Zhang 96214ffae0SHongbo Zhang out_be32(&scfg->pmcintlecr, 0); 97214ffae0SHongbo Zhang /* Clear PMC interrupt status */ 98214ffae0SHongbo Zhang out_be32(&scfg->pmcintsr, 0xffffffff); 99214ffae0SHongbo Zhang /* Enable wakeup interrupt during deep sleep */ 100214ffae0SHongbo Zhang out_be32(&scfg->pmcintecr, pmcintecr); 101214ffae0SHongbo Zhang } 102214ffae0SHongbo Zhang 103214ffae0SHongbo Zhang static void __secure ls1_delay(unsigned int loop) 104214ffae0SHongbo Zhang { 105214ffae0SHongbo Zhang while (loop--) { 106214ffae0SHongbo Zhang int i = 1000; 107214ffae0SHongbo Zhang while (i--) 108214ffae0SHongbo Zhang ; 109214ffae0SHongbo Zhang } 110214ffae0SHongbo Zhang } 111214ffae0SHongbo Zhang 112214ffae0SHongbo Zhang static void __secure ls1_start_fsm(void) 113214ffae0SHongbo Zhang { 114214ffae0SHongbo Zhang void *dcsr_epu_base = (void *)(CONFIG_SYS_DCSRBAR + EPU_BLOCK_OFFSET); 115295a24b3SYork Sun void *ccsr_gic_base = (void *)SYS_FSL_GIC_ADDR; 116214ffae0SHongbo Zhang struct ccsr_scfg __iomem *scfg = (void *)CONFIG_SYS_FSL_SCFG_ADDR; 117214ffae0SHongbo Zhang struct ccsr_ddr __iomem *ddr = (void *)CONFIG_SYS_FSL_DDR_ADDR; 118214ffae0SHongbo Zhang 119214ffae0SHongbo Zhang /* Set HRSTCR */ 120214ffae0SHongbo Zhang setbits_be32(&scfg->hrstcr, 0x80000000); 121214ffae0SHongbo Zhang 122214ffae0SHongbo Zhang /* Place DDR controller in self refresh mode */ 123214ffae0SHongbo Zhang setbits_be32(&ddr->sdram_cfg_2, 0x80000000); 124214ffae0SHongbo Zhang 125214ffae0SHongbo Zhang ls1_delay(2000); 126214ffae0SHongbo Zhang 127214ffae0SHongbo Zhang /* Set EVT4_B to lock the signal MCKE down */ 128214ffae0SHongbo Zhang out_be32(dcsr_epu_base + EPECR0, 0x0); 129214ffae0SHongbo Zhang 130214ffae0SHongbo Zhang ls1_delay(2000); 131214ffae0SHongbo Zhang 132214ffae0SHongbo Zhang out_be32(ccsr_gic_base + CCSR_GICD_CTLR, 0x0); 133214ffae0SHongbo Zhang out_be32(ccsr_gic_base + CCSR_GICC_CTLR, 0x0); 134214ffae0SHongbo Zhang 135214ffae0SHongbo Zhang /* Enable all EPU Counters */ 136214ffae0SHongbo Zhang setbits_be32(dcsr_epu_base + EPGCR, 0x80000000); 137214ffae0SHongbo Zhang 138214ffae0SHongbo Zhang /* Enable SCU15 */ 139214ffae0SHongbo Zhang setbits_be32(dcsr_epu_base + EPECR15, 0x90000004); 140214ffae0SHongbo Zhang 141214ffae0SHongbo Zhang /* Enter WFI mode, and EPU FSM will start */ 142214ffae0SHongbo Zhang __asm__ __volatile__ ("wfi" : : : "memory"); 143214ffae0SHongbo Zhang 144214ffae0SHongbo Zhang /* NEVER ENTER HERE */ 145214ffae0SHongbo Zhang while (1) 146214ffae0SHongbo Zhang ; 147214ffae0SHongbo Zhang } 148214ffae0SHongbo Zhang 149214ffae0SHongbo Zhang static void __secure ls1_deep_sleep(u32 entry_point) 150214ffae0SHongbo Zhang { 151214ffae0SHongbo Zhang struct ccsr_scfg __iomem *scfg = (void *)CONFIG_SYS_FSL_SCFG_ADDR; 152214ffae0SHongbo Zhang struct ccsr_gur __iomem *gur = (void *)CONFIG_SYS_FSL_GUTS_ADDR; 153214ffae0SHongbo Zhang struct ccsr_rcpm __iomem *rcpm = (void *)CONFIG_SYS_FSL_RCPM_ADDR; 154214ffae0SHongbo Zhang #ifdef QIXIS_BASE 155214ffae0SHongbo Zhang u32 tmp; 156214ffae0SHongbo Zhang void *qixis_base = (void *)QIXIS_BASE; 157214ffae0SHongbo Zhang #endif 158214ffae0SHongbo Zhang 159214ffae0SHongbo Zhang /* Enable cluster to enter the PCL10 state */ 160214ffae0SHongbo Zhang out_be32(&scfg->clusterpmcr, SCFG_CLUSTERPMCR_WFIL2EN); 161214ffae0SHongbo Zhang 162214ffae0SHongbo Zhang /* Save the first 128 bytes of DDR data */ 163214ffae0SHongbo Zhang ls1_save_ddr_head(); 164214ffae0SHongbo Zhang 165214ffae0SHongbo Zhang /* Save the kernel resume entry */ 166214ffae0SHongbo Zhang out_le32(&scfg->sparecr[3], entry_point); 167214ffae0SHongbo Zhang 168214ffae0SHongbo Zhang /* Request to put cluster 0 in PCL10 state */ 169214ffae0SHongbo Zhang setbits_be32(&rcpm->clpcl10setr, RCPM_CLPCL10SETR_C0); 170214ffae0SHongbo Zhang 171214ffae0SHongbo Zhang /* Setup the registers of the EPU FSM for deep sleep */ 172214ffae0SHongbo Zhang ls1_fsm_setup(); 173214ffae0SHongbo Zhang 174214ffae0SHongbo Zhang #ifdef QIXIS_BASE 175214ffae0SHongbo Zhang /* Connect the EVENT button to IRQ in FPGA */ 176214ffae0SHongbo Zhang tmp = in_8(qixis_base + QIXIS_CTL_SYS); 177214ffae0SHongbo Zhang tmp &= ~QIXIS_CTL_SYS_EVTSW_MASK; 178214ffae0SHongbo Zhang tmp |= QIXIS_CTL_SYS_EVTSW_IRQ; 179214ffae0SHongbo Zhang out_8(qixis_base + QIXIS_CTL_SYS, tmp); 180214ffae0SHongbo Zhang 181214ffae0SHongbo Zhang /* Enable deep sleep signals in FPGA */ 182214ffae0SHongbo Zhang tmp = in_8(qixis_base + QIXIS_PWR_CTL2); 183214ffae0SHongbo Zhang tmp |= QIXIS_PWR_CTL2_PCTL; 184214ffae0SHongbo Zhang out_8(qixis_base + QIXIS_PWR_CTL2, tmp); 185214ffae0SHongbo Zhang 186214ffae0SHongbo Zhang /* Pull down PCIe RST# */ 187214ffae0SHongbo Zhang tmp = in_8(qixis_base + QIXIS_RST_FORCE_3); 188214ffae0SHongbo Zhang tmp |= QIXIS_RST_FORCE_3_PCIESLOT1; 189214ffae0SHongbo Zhang out_8(qixis_base + QIXIS_RST_FORCE_3, tmp); 190214ffae0SHongbo Zhang #endif 191214ffae0SHongbo Zhang 192214ffae0SHongbo Zhang /* Enable Warm Device Reset */ 193214ffae0SHongbo Zhang setbits_be32(&scfg->dpslpcr, SCFG_DPSLPCR_WDRR_EN); 194214ffae0SHongbo Zhang setbits_be32(&gur->crstsr, DCFG_CRSTSR_WDRFR); 195214ffae0SHongbo Zhang 196*26cbc0d6SRan Wang /* Disable QE */ 197*26cbc0d6SRan Wang setbits_be32(&gur->devdisr, CCSR_DEVDISR1_QE); 198*26cbc0d6SRan Wang 199214ffae0SHongbo Zhang ls1_deepsleep_irq_cfg(); 200214ffae0SHongbo Zhang 201214ffae0SHongbo Zhang psci_v7_flush_dcache_all(); 202214ffae0SHongbo Zhang 203214ffae0SHongbo Zhang ls1_start_fsm(); 204214ffae0SHongbo Zhang } 205214ffae0SHongbo Zhang 206214ffae0SHongbo Zhang #else 207214ffae0SHongbo Zhang static void __secure ls1_sleep(void) 208214ffae0SHongbo Zhang { 209214ffae0SHongbo Zhang struct ccsr_scfg __iomem *scfg = (void *)CONFIG_SYS_FSL_SCFG_ADDR; 210214ffae0SHongbo Zhang struct ccsr_rcpm __iomem *rcpm = (void *)CONFIG_SYS_FSL_RCPM_ADDR; 211214ffae0SHongbo Zhang 212214ffae0SHongbo Zhang #ifdef QIXIS_BASE 213214ffae0SHongbo Zhang u32 tmp; 214214ffae0SHongbo Zhang void *qixis_base = (void *)QIXIS_BASE; 215214ffae0SHongbo Zhang 216214ffae0SHongbo Zhang /* Connect the EVENT button to IRQ in FPGA */ 217214ffae0SHongbo Zhang tmp = in_8(qixis_base + QIXIS_CTL_SYS); 218214ffae0SHongbo Zhang tmp &= ~QIXIS_CTL_SYS_EVTSW_MASK; 219214ffae0SHongbo Zhang tmp |= QIXIS_CTL_SYS_EVTSW_IRQ; 220214ffae0SHongbo Zhang out_8(qixis_base + QIXIS_CTL_SYS, tmp); 221214ffae0SHongbo Zhang #endif 222214ffae0SHongbo Zhang 223214ffae0SHongbo Zhang /* Enable cluster to enter the PCL10 state */ 224214ffae0SHongbo Zhang out_be32(&scfg->clusterpmcr, SCFG_CLUSTERPMCR_WFIL2EN); 225214ffae0SHongbo Zhang 226214ffae0SHongbo Zhang setbits_be32(&rcpm->powmgtcsr, RCPM_POWMGTCSR_LPM20_REQ); 227214ffae0SHongbo Zhang 228214ffae0SHongbo Zhang __asm__ __volatile__ ("wfi" : : : "memory"); 229214ffae0SHongbo Zhang } 230214ffae0SHongbo Zhang #endif 231214ffae0SHongbo Zhang 232214ffae0SHongbo Zhang void __secure ls1_system_suspend(u32 fn, u32 entry_point, u32 context_id) 233214ffae0SHongbo Zhang { 234214ffae0SHongbo Zhang #ifdef CONFIG_LS1_DEEP_SLEEP 235214ffae0SHongbo Zhang ls1_deep_sleep(entry_point); 236214ffae0SHongbo Zhang #else 237214ffae0SHongbo Zhang ls1_sleep(); 238214ffae0SHongbo Zhang #endif 239214ffae0SHongbo Zhang } 240