1 /* 2 * Copyright 2014 Freescale Semiconductor, Inc. 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 #ifndef __FSL_EPU_H 8 #define __FSL_EPU_H 9 10 #include <asm/types.h> 11 12 #define FSL_STRIDE_4B 4 13 #define FSL_STRIDE_8B 8 14 15 /* Block offsets */ 16 #define EPU_BLOCK_OFFSET 0x00000000 17 18 /* EPGCR (Event Processor Global Control Register) */ 19 #define EPGCR 0x000 20 21 /* EPEVTCR0-9 (Event Processor EVT Pin Control Registers) */ 22 #define EPEVTCR0 0x050 23 #define EPEVTCR9 0x074 24 #define EPEVTCR_STRIDE FSL_STRIDE_4B 25 26 /* EPXTRIGCR (Event Processor Crosstrigger Control Register) */ 27 #define EPXTRIGCR 0x090 28 29 /* EPIMCR0-31 (Event Processor Input Mux Control Registers) */ 30 #define EPIMCR0 0x100 31 #define EPIMCR31 0x17C 32 #define EPIMCR_STRIDE FSL_STRIDE_4B 33 34 /* EPSMCR0-15 (Event Processor SCU Mux Control Registers) */ 35 #define EPSMCR0 0x200 36 #define EPSMCR15 0x278 37 #define EPSMCR_STRIDE FSL_STRIDE_8B 38 39 /* EPECR0-15 (Event Processor Event Control Registers) */ 40 #define EPECR0 0x300 41 #define EPECR15 0x33C 42 #define EPECR_STRIDE FSL_STRIDE_4B 43 44 /* EPACR0-15 (Event Processor Action Control Registers) */ 45 #define EPACR0 0x400 46 #define EPACR15 0x43C 47 #define EPACR_STRIDE FSL_STRIDE_4B 48 49 /* EPCCRi0-15 (Event Processor Counter Control Registers) */ 50 #define EPCCR0 0x800 51 #define EPCCR15 0x83C 52 #define EPCCR31 0x87C 53 #define EPCCR_STRIDE FSL_STRIDE_4B 54 55 /* EPCMPR0-15 (Event Processor Counter Compare Registers) */ 56 #define EPCMPR0 0x900 57 #define EPCMPR15 0x93C 58 #define EPCMPR31 0x97C 59 #define EPCMPR_STRIDE FSL_STRIDE_4B 60 61 /* EPCTR0-31 (Event Processor Counter Register) */ 62 #define EPCTR0 0xA00 63 #define EPCTR31 0xA7C 64 #define EPCTR_STRIDE FSL_STRIDE_4B 65 66 #define FSM_END_FLAG 0xFFFFFFFFUL 67 68 struct fsm_reg_vals { 69 u32 offset; 70 u32 value; 71 }; 72 73 void fsl_epu_setup(void *epu_base); 74 void fsl_epu_clean(void *epu_base); 75 76 #endif 77