1*306fa012Schenhui zhao /* 2*306fa012Schenhui zhao * Copyright 2014 Freescale Semiconductor, Inc. 3*306fa012Schenhui zhao * 4*306fa012Schenhui zhao * SPDX-License-Identifier: GPL-2.0+ 5*306fa012Schenhui zhao */ 6*306fa012Schenhui zhao 7*306fa012Schenhui zhao #ifndef __FSL_EPU_H 8*306fa012Schenhui zhao #define __FSL_EPU_H 9*306fa012Schenhui zhao 10*306fa012Schenhui zhao #include <asm/types.h> 11*306fa012Schenhui zhao 12*306fa012Schenhui zhao #define FSL_STRIDE_4B 4 13*306fa012Schenhui zhao #define FSL_STRIDE_8B 8 14*306fa012Schenhui zhao 15*306fa012Schenhui zhao /* Block offsets */ 16*306fa012Schenhui zhao #define EPU_BLOCK_OFFSET 0x00000000 17*306fa012Schenhui zhao 18*306fa012Schenhui zhao /* EPGCR (Event Processor Global Control Register) */ 19*306fa012Schenhui zhao #define EPGCR 0x000 20*306fa012Schenhui zhao 21*306fa012Schenhui zhao /* EPEVTCR0-9 (Event Processor EVT Pin Control Registers) */ 22*306fa012Schenhui zhao #define EPEVTCR0 0x050 23*306fa012Schenhui zhao #define EPEVTCR9 0x074 24*306fa012Schenhui zhao #define EPEVTCR_STRIDE FSL_STRIDE_4B 25*306fa012Schenhui zhao 26*306fa012Schenhui zhao /* EPXTRIGCR (Event Processor Crosstrigger Control Register) */ 27*306fa012Schenhui zhao #define EPXTRIGCR 0x090 28*306fa012Schenhui zhao 29*306fa012Schenhui zhao /* EPIMCR0-31 (Event Processor Input Mux Control Registers) */ 30*306fa012Schenhui zhao #define EPIMCR0 0x100 31*306fa012Schenhui zhao #define EPIMCR31 0x17C 32*306fa012Schenhui zhao #define EPIMCR_STRIDE FSL_STRIDE_4B 33*306fa012Schenhui zhao 34*306fa012Schenhui zhao /* EPSMCR0-15 (Event Processor SCU Mux Control Registers) */ 35*306fa012Schenhui zhao #define EPSMCR0 0x200 36*306fa012Schenhui zhao #define EPSMCR15 0x278 37*306fa012Schenhui zhao #define EPSMCR_STRIDE FSL_STRIDE_8B 38*306fa012Schenhui zhao 39*306fa012Schenhui zhao /* EPECR0-15 (Event Processor Event Control Registers) */ 40*306fa012Schenhui zhao #define EPECR0 0x300 41*306fa012Schenhui zhao #define EPECR15 0x33C 42*306fa012Schenhui zhao #define EPECR_STRIDE FSL_STRIDE_4B 43*306fa012Schenhui zhao 44*306fa012Schenhui zhao /* EPACR0-15 (Event Processor Action Control Registers) */ 45*306fa012Schenhui zhao #define EPACR0 0x400 46*306fa012Schenhui zhao #define EPACR15 0x43C 47*306fa012Schenhui zhao #define EPACR_STRIDE FSL_STRIDE_4B 48*306fa012Schenhui zhao 49*306fa012Schenhui zhao /* EPCCRi0-15 (Event Processor Counter Control Registers) */ 50*306fa012Schenhui zhao #define EPCCR0 0x800 51*306fa012Schenhui zhao #define EPCCR15 0x83C 52*306fa012Schenhui zhao #define EPCCR31 0x87C 53*306fa012Schenhui zhao #define EPCCR_STRIDE FSL_STRIDE_4B 54*306fa012Schenhui zhao 55*306fa012Schenhui zhao /* EPCMPR0-15 (Event Processor Counter Compare Registers) */ 56*306fa012Schenhui zhao #define EPCMPR0 0x900 57*306fa012Schenhui zhao #define EPCMPR15 0x93C 58*306fa012Schenhui zhao #define EPCMPR31 0x97C 59*306fa012Schenhui zhao #define EPCMPR_STRIDE FSL_STRIDE_4B 60*306fa012Schenhui zhao 61*306fa012Schenhui zhao /* EPCTR0-31 (Event Processor Counter Register) */ 62*306fa012Schenhui zhao #define EPCTR0 0xA00 63*306fa012Schenhui zhao #define EPCTR31 0xA7C 64*306fa012Schenhui zhao #define EPCTR_STRIDE FSL_STRIDE_4B 65*306fa012Schenhui zhao 66*306fa012Schenhui zhao void fsl_epu_clean(void *epu_base); 67*306fa012Schenhui zhao 68*306fa012Schenhui zhao #endif 69