1 /* 2 * Copyright 2014 Freescale Semiconductor, Inc. 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 #include <common.h> 8 #include <asm/io.h> 9 10 #include "fsl_epu.h" 11 12 struct fsm_reg_vals epu_default_val[] = { 13 /* EPGCR (Event Processor Global Control Register) */ 14 {EPGCR, 0}, 15 /* EPECR (Event Processor Event Control Registers) */ 16 {EPECR0 + EPECR_STRIDE * 0, 0}, 17 {EPECR0 + EPECR_STRIDE * 1, 0}, 18 {EPECR0 + EPECR_STRIDE * 2, 0xF0004004}, 19 {EPECR0 + EPECR_STRIDE * 3, 0x80000084}, 20 {EPECR0 + EPECR_STRIDE * 4, 0x20000084}, 21 {EPECR0 + EPECR_STRIDE * 5, 0x08000004}, 22 {EPECR0 + EPECR_STRIDE * 6, 0x80000084}, 23 {EPECR0 + EPECR_STRIDE * 7, 0x80000084}, 24 {EPECR0 + EPECR_STRIDE * 8, 0x60000084}, 25 {EPECR0 + EPECR_STRIDE * 9, 0x08000084}, 26 {EPECR0 + EPECR_STRIDE * 10, 0x42000084}, 27 {EPECR0 + EPECR_STRIDE * 11, 0x90000084}, 28 {EPECR0 + EPECR_STRIDE * 12, 0x80000084}, 29 {EPECR0 + EPECR_STRIDE * 13, 0x08000084}, 30 {EPECR0 + EPECR_STRIDE * 14, 0x02000084}, 31 {EPECR0 + EPECR_STRIDE * 15, 0x00000004}, 32 /* 33 * EPEVTCR (Event Processor EVT Pin Control Registers) 34 * SCU8 triger EVT2, and SCU11 triger EVT9 35 */ 36 {EPEVTCR0 + EPEVTCR_STRIDE * 0, 0}, 37 {EPEVTCR0 + EPEVTCR_STRIDE * 1, 0}, 38 {EPEVTCR0 + EPEVTCR_STRIDE * 2, 0x80000001}, 39 {EPEVTCR0 + EPEVTCR_STRIDE * 3, 0}, 40 {EPEVTCR0 + EPEVTCR_STRIDE * 4, 0}, 41 {EPEVTCR0 + EPEVTCR_STRIDE * 5, 0}, 42 {EPEVTCR0 + EPEVTCR_STRIDE * 6, 0}, 43 {EPEVTCR0 + EPEVTCR_STRIDE * 7, 0}, 44 {EPEVTCR0 + EPEVTCR_STRIDE * 8, 0}, 45 {EPEVTCR0 + EPEVTCR_STRIDE * 9, 0xB0000001}, 46 /* EPCMPR (Event Processor Counter Compare Registers) */ 47 {EPCMPR0 + EPCMPR_STRIDE * 0, 0}, 48 {EPCMPR0 + EPCMPR_STRIDE * 1, 0}, 49 {EPCMPR0 + EPCMPR_STRIDE * 2, 0x000000FF}, 50 {EPCMPR0 + EPCMPR_STRIDE * 3, 0}, 51 {EPCMPR0 + EPCMPR_STRIDE * 4, 0x000000FF}, 52 {EPCMPR0 + EPCMPR_STRIDE * 5, 0x00000020}, 53 {EPCMPR0 + EPCMPR_STRIDE * 6, 0}, 54 {EPCMPR0 + EPCMPR_STRIDE * 7, 0}, 55 {EPCMPR0 + EPCMPR_STRIDE * 8, 0x000000FF}, 56 {EPCMPR0 + EPCMPR_STRIDE * 9, 0x000000FF}, 57 {EPCMPR0 + EPCMPR_STRIDE * 10, 0x000000FF}, 58 {EPCMPR0 + EPCMPR_STRIDE * 11, 0x000000FF}, 59 {EPCMPR0 + EPCMPR_STRIDE * 12, 0x000000FF}, 60 {EPCMPR0 + EPCMPR_STRIDE * 13, 0}, 61 {EPCMPR0 + EPCMPR_STRIDE * 14, 0x000000FF}, 62 {EPCMPR0 + EPCMPR_STRIDE * 15, 0x000000FF}, 63 /* EPCCR (Event Processor Counter Control Registers) */ 64 {EPCCR0 + EPCCR_STRIDE * 0, 0}, 65 {EPCCR0 + EPCCR_STRIDE * 1, 0}, 66 {EPCCR0 + EPCCR_STRIDE * 2, 0x92840000}, 67 {EPCCR0 + EPCCR_STRIDE * 3, 0}, 68 {EPCCR0 + EPCCR_STRIDE * 4, 0x92840000}, 69 {EPCCR0 + EPCCR_STRIDE * 5, 0x92840000}, 70 {EPCCR0 + EPCCR_STRIDE * 6, 0}, 71 {EPCCR0 + EPCCR_STRIDE * 7, 0}, 72 {EPCCR0 + EPCCR_STRIDE * 8, 0x92840000}, 73 {EPCCR0 + EPCCR_STRIDE * 9, 0x92840000}, 74 {EPCCR0 + EPCCR_STRIDE * 10, 0x92840000}, 75 {EPCCR0 + EPCCR_STRIDE * 11, 0x92840000}, 76 {EPCCR0 + EPCCR_STRIDE * 12, 0x92840000}, 77 {EPCCR0 + EPCCR_STRIDE * 13, 0}, 78 {EPCCR0 + EPCCR_STRIDE * 14, 0x92840000}, 79 {EPCCR0 + EPCCR_STRIDE * 15, 0x92840000}, 80 /* EPSMCR (Event Processor SCU Mux Control Registers) */ 81 {EPSMCR0 + EPSMCR_STRIDE * 0, 0}, 82 {EPSMCR0 + EPSMCR_STRIDE * 1, 0}, 83 {EPSMCR0 + EPSMCR_STRIDE * 2, 0x6C700000}, 84 {EPSMCR0 + EPSMCR_STRIDE * 3, 0x2F000000}, 85 {EPSMCR0 + EPSMCR_STRIDE * 4, 0x002F0000}, 86 {EPSMCR0 + EPSMCR_STRIDE * 5, 0x00002E00}, 87 {EPSMCR0 + EPSMCR_STRIDE * 6, 0x7C000000}, 88 {EPSMCR0 + EPSMCR_STRIDE * 7, 0x30000000}, 89 {EPSMCR0 + EPSMCR_STRIDE * 8, 0x64300000}, 90 {EPSMCR0 + EPSMCR_STRIDE * 9, 0x00003000}, 91 {EPSMCR0 + EPSMCR_STRIDE * 10, 0x65000030}, 92 {EPSMCR0 + EPSMCR_STRIDE * 11, 0x31740000}, 93 {EPSMCR0 + EPSMCR_STRIDE * 12, 0x7F000000}, 94 {EPSMCR0 + EPSMCR_STRIDE * 13, 0x00003100}, 95 {EPSMCR0 + EPSMCR_STRIDE * 14, 0x00000031}, 96 {EPSMCR0 + EPSMCR_STRIDE * 15, 0x76000000}, 97 /* EPACR (Event Processor Action Control Registers) */ 98 {EPACR0 + EPACR_STRIDE * 0, 0}, 99 {EPACR0 + EPACR_STRIDE * 1, 0}, 100 {EPACR0 + EPACR_STRIDE * 2, 0}, 101 {EPACR0 + EPACR_STRIDE * 3, 0x00000080}, 102 {EPACR0 + EPACR_STRIDE * 4, 0}, 103 {EPACR0 + EPACR_STRIDE * 5, 0x00000040}, 104 {EPACR0 + EPACR_STRIDE * 6, 0}, 105 {EPACR0 + EPACR_STRIDE * 7, 0}, 106 {EPACR0 + EPACR_STRIDE * 8, 0}, 107 {EPACR0 + EPACR_STRIDE * 9, 0x0000001C}, 108 {EPACR0 + EPACR_STRIDE * 10, 0x00000020}, 109 {EPACR0 + EPACR_STRIDE * 11, 0}, 110 {EPACR0 + EPACR_STRIDE * 12, 0x00000003}, 111 {EPACR0 + EPACR_STRIDE * 13, 0x06000000}, 112 {EPACR0 + EPACR_STRIDE * 14, 0x04000000}, 113 {EPACR0 + EPACR_STRIDE * 15, 0x02000000}, 114 /* EPIMCR (Event Processor Input Mux Control Registers) */ 115 {EPIMCR0 + EPIMCR_STRIDE * 0, 0}, 116 {EPIMCR0 + EPIMCR_STRIDE * 1, 0}, 117 {EPIMCR0 + EPIMCR_STRIDE * 2, 0}, 118 {EPIMCR0 + EPIMCR_STRIDE * 3, 0}, 119 {EPIMCR0 + EPIMCR_STRIDE * 4, 0x44000000}, 120 {EPIMCR0 + EPIMCR_STRIDE * 5, 0x40000000}, 121 {EPIMCR0 + EPIMCR_STRIDE * 6, 0}, 122 {EPIMCR0 + EPIMCR_STRIDE * 7, 0}, 123 {EPIMCR0 + EPIMCR_STRIDE * 8, 0}, 124 {EPIMCR0 + EPIMCR_STRIDE * 9, 0}, 125 {EPIMCR0 + EPIMCR_STRIDE * 10, 0}, 126 {EPIMCR0 + EPIMCR_STRIDE * 11, 0}, 127 {EPIMCR0 + EPIMCR_STRIDE * 12, 0x44000000}, 128 {EPIMCR0 + EPIMCR_STRIDE * 13, 0}, 129 {EPIMCR0 + EPIMCR_STRIDE * 14, 0}, 130 {EPIMCR0 + EPIMCR_STRIDE * 15, 0}, 131 {EPIMCR0 + EPIMCR_STRIDE * 16, 0x6A000000}, 132 {EPIMCR0 + EPIMCR_STRIDE * 17, 0}, 133 {EPIMCR0 + EPIMCR_STRIDE * 18, 0}, 134 {EPIMCR0 + EPIMCR_STRIDE * 19, 0}, 135 {EPIMCR0 + EPIMCR_STRIDE * 20, 0x48000000}, 136 {EPIMCR0 + EPIMCR_STRIDE * 21, 0}, 137 {EPIMCR0 + EPIMCR_STRIDE * 22, 0x6C000000}, 138 {EPIMCR0 + EPIMCR_STRIDE * 23, 0}, 139 {EPIMCR0 + EPIMCR_STRIDE * 24, 0}, 140 {EPIMCR0 + EPIMCR_STRIDE * 25, 0}, 141 {EPIMCR0 + EPIMCR_STRIDE * 26, 0}, 142 {EPIMCR0 + EPIMCR_STRIDE * 27, 0}, 143 {EPIMCR0 + EPIMCR_STRIDE * 28, 0x76000000}, 144 {EPIMCR0 + EPIMCR_STRIDE * 29, 0}, 145 {EPIMCR0 + EPIMCR_STRIDE * 30, 0}, 146 {EPIMCR0 + EPIMCR_STRIDE * 31, 0x76000000}, 147 /* EPXTRIGCR (Event Processor Crosstrigger Control Register) */ 148 {EPXTRIGCR, 0x0000FFDF}, 149 /* end */ 150 {FSM_END_FLAG, 0}, 151 }; 152 153 /** 154 * fsl_epu_setup - Setup EPU registers to default values 155 */ 156 void fsl_epu_setup(void *epu_base) 157 { 158 struct fsm_reg_vals *data = epu_default_val; 159 160 if (!epu_base || !data) 161 return; 162 163 while (data->offset != FSM_END_FLAG) { 164 out_be32(epu_base + data->offset, data->value); 165 data++; 166 } 167 } 168 169 /** 170 * fsl_epu_clean - Clear EPU registers 171 */ 172 void fsl_epu_clean(void *epu_base) 173 { 174 u32 offset; 175 176 /* follow the exact sequence to clear the registers */ 177 /* Clear EPACRn */ 178 for (offset = EPACR0; offset <= EPACR15; offset += EPACR_STRIDE) 179 out_be32(epu_base + offset, 0); 180 181 /* Clear EPEVTCRn */ 182 for (offset = EPEVTCR0; offset <= EPEVTCR9; offset += EPEVTCR_STRIDE) 183 out_be32(epu_base + offset, 0); 184 185 /* Clear EPGCR */ 186 out_be32(epu_base + EPGCR, 0); 187 188 /* Clear EPSMCRn */ 189 for (offset = EPSMCR0; offset <= EPSMCR15; offset += EPSMCR_STRIDE) 190 out_be32(epu_base + offset, 0); 191 192 /* Clear EPCCRn */ 193 for (offset = EPCCR0; offset <= EPCCR31; offset += EPCCR_STRIDE) 194 out_be32(epu_base + offset, 0); 195 196 /* Clear EPCMPRn */ 197 for (offset = EPCMPR0; offset <= EPCMPR31; offset += EPCMPR_STRIDE) 198 out_be32(epu_base + offset, 0); 199 200 /* Clear EPCTRn */ 201 for (offset = EPCTR0; offset <= EPCTR31; offset += EPCTR_STRIDE) 202 out_be32(epu_base + offset, 0); 203 204 /* Clear EPIMCRn */ 205 for (offset = EPIMCR0; offset <= EPIMCR31; offset += EPIMCR_STRIDE) 206 out_be32(epu_base + offset, 0); 207 208 /* Clear EPXTRIGCRn */ 209 out_be32(epu_base + EPXTRIGCR, 0); 210 211 /* Clear EPECRn */ 212 for (offset = EPECR0; offset <= EPECR15; offset += EPECR_STRIDE) 213 out_be32(epu_base + offset, 0); 214 } 215