1 /* 2 * Copyright 2014 Freescale Semiconductor, Inc. 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 #include <common.h> 8 #include <libfdt.h> 9 #include <fdt_support.h> 10 #include <asm/io.h> 11 #include <asm/processor.h> 12 #include <asm/arch/clock.h> 13 #include <linux/ctype.h> 14 #ifdef CONFIG_FSL_ESDHC 15 #include <fsl_esdhc.h> 16 #endif 17 #include <tsec.h> 18 #include <asm/arch/immap_ls102xa.h> 19 #include <fsl_sec.h> 20 21 DECLARE_GLOBAL_DATA_PTR; 22 23 void ft_fixup_enet_phy_connect_type(void *fdt) 24 { 25 struct eth_device *dev; 26 struct tsec_private *priv; 27 const char *enet_path, *phy_path; 28 char enet[16]; 29 char phy[16]; 30 int phy_node; 31 int i = 0; 32 int enet_id = 0; 33 uint32_t ph; 34 35 while ((dev = eth_get_dev_by_index(i++)) != NULL) { 36 if (strstr(dev->name, "eTSEC1")) 37 enet_id = 0; 38 else if (strstr(dev->name, "eTSEC2")) 39 enet_id = 1; 40 else if (strstr(dev->name, "eTSEC3")) 41 enet_id = 2; 42 else 43 continue; 44 45 priv = dev->priv; 46 if (priv->flags & TSEC_SGMII) 47 continue; 48 49 sprintf(enet, "ethernet%d", enet_id); 50 enet_path = fdt_get_alias(fdt, enet); 51 if (!enet_path) 52 continue; 53 54 sprintf(phy, "enet%d_rgmii_phy", enet_id); 55 phy_path = fdt_get_alias(fdt, phy); 56 if (!phy_path) 57 continue; 58 59 phy_node = fdt_path_offset(fdt, phy_path); 60 if (phy_node < 0) 61 continue; 62 63 ph = fdt_create_phandle(fdt, phy_node); 64 if (ph) 65 do_fixup_by_path_u32(fdt, enet_path, 66 "phy-handle", ph, 1); 67 68 do_fixup_by_path(fdt, enet_path, "phy-connection-type", 69 phy_string_for_interface( 70 PHY_INTERFACE_MODE_RGMII_ID), 71 sizeof(phy_string_for_interface( 72 PHY_INTERFACE_MODE_RGMII_ID)), 73 1); 74 } 75 } 76 77 void ft_cpu_setup(void *blob, bd_t *bd) 78 { 79 int off; 80 int val; 81 const char *sysclk_path; 82 struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR); 83 unsigned int svr; 84 svr = in_be32(&gur->svr); 85 86 unsigned long busclk = get_bus_freq(0); 87 88 /* delete crypto node if not on an E-processor */ 89 if (!IS_E_PROCESSOR(svr)) 90 fdt_fixup_crypto_node(blob, 0); 91 #if CONFIG_SYS_FSL_SEC_COMPAT >= 4 92 else { 93 ccsr_sec_t __iomem *sec; 94 95 sec = (void __iomem *)CONFIG_SYS_FSL_SEC_ADDR; 96 fdt_fixup_crypto_node(blob, sec_in32(&sec->secvid_ms)); 97 } 98 #endif 99 100 fdt_fixup_ethernet(blob); 101 102 off = fdt_node_offset_by_prop_value(blob, -1, "device_type", "cpu", 4); 103 while (off != -FDT_ERR_NOTFOUND) { 104 val = gd->cpu_clk; 105 fdt_setprop(blob, off, "clock-frequency", &val, 4); 106 off = fdt_node_offset_by_prop_value(blob, off, 107 "device_type", "cpu", 4); 108 } 109 110 do_fixup_by_prop_u32(blob, "device_type", "soc", 111 4, "bus-frequency", busclk, 1); 112 113 ft_fixup_enet_phy_connect_type(blob); 114 115 #ifdef CONFIG_SYS_NS16550 116 do_fixup_by_compat_u32(blob, "fsl,16550-FIFO64", 117 "clock-frequency", CONFIG_SYS_NS16550_CLK, 1); 118 #endif 119 120 sysclk_path = fdt_get_alias(blob, "sysclk"); 121 if (sysclk_path) 122 do_fixup_by_path_u32(blob, sysclk_path, "clock-frequency", 123 CONFIG_SYS_CLK_FREQ, 1); 124 do_fixup_by_compat_u32(blob, "fsl,qoriq-sysclk-2.0", 125 "clock-frequency", CONFIG_SYS_CLK_FREQ, 1); 126 127 #if defined(CONFIG_DEEP_SLEEP) && defined(CONFIG_SD_BOOT) 128 #define UBOOT_HEAD_LEN 0x1000 129 /* 130 * Reserved memory in SD boot deep sleep case. 131 * Second stage uboot binary and malloc space should be reserved. 132 * If the memory they occupied has not been reserved, then this 133 * space would be used by kernel and overwritten in uboot when 134 * deep sleep resume, which cause deep sleep failed. 135 * Since second uboot binary has a head, that space need to be 136 * reserved either(assuming its size is less than 0x1000). 137 */ 138 off = fdt_add_mem_rsv(blob, CONFIG_SYS_TEXT_BASE - UBOOT_HEAD_LEN, 139 CONFIG_SYS_MONITOR_LEN + CONFIG_SYS_SPL_MALLOC_SIZE + 140 UBOOT_HEAD_LEN); 141 if (off < 0) 142 printf("Failed to reserve memory for SD boot deep sleep: %s\n", 143 fdt_strerror(off)); 144 #endif 145 146 #if defined(CONFIG_FSL_ESDHC) 147 fdt_fixup_esdhc(blob, bd); 148 #endif 149 150 /* 151 * platform bus clock = system bus clock/2 152 * Here busclk = system bus clock 153 * We are using the platform bus clock as 1588 Timer reference 154 * clock source select 155 */ 156 do_fixup_by_compat_u32(blob, "fsl, gianfar-ptp-timer", 157 "timer-frequency", busclk / 2, 1); 158 159 /* 160 * clock-freq should change to clock-frequency and 161 * flexcan-v1.0 should change to p1010-flexcan respectively 162 * in the future. 163 */ 164 do_fixup_by_compat_u32(blob, "fsl, flexcan-v1.0", 165 "clock_freq", busclk / 2, 1); 166 167 do_fixup_by_compat_u32(blob, "fsl, flexcan-v1.0", 168 "clock-frequency", busclk / 2, 1); 169 170 do_fixup_by_compat_u32(blob, "fsl, ls1021a-flexcan", 171 "clock-frequency", busclk / 2, 1); 172 173 #ifdef CONFIG_QSPI_BOOT 174 off = fdt_node_offset_by_compat_reg(blob, FSL_IFC_COMPAT, 175 CONFIG_SYS_IFC_ADDR); 176 fdt_set_node_status(blob, off, FDT_STATUS_DISABLED, 0); 177 #else 178 off = fdt_node_offset_by_compat_reg(blob, FSL_QSPI_COMPAT, 179 QSPI0_BASE_ADDR); 180 fdt_set_node_status(blob, off, FDT_STATUS_DISABLED, 0); 181 off = fdt_node_offset_by_compat_reg(blob, FSL_DSPI_COMPAT, 182 DSPI1_BASE_ADDR); 183 fdt_set_node_status(blob, off, FDT_STATUS_DISABLED, 0); 184 #endif 185 } 186