1 // SPDX-License-Identifier: GPL-2.0+ 2 /* 3 * Copyright 2014 Freescale Semiconductor, Inc. 4 */ 5 6 #include <common.h> 7 #include <linux/libfdt.h> 8 #include <fdt_support.h> 9 #include <asm/io.h> 10 #include <asm/processor.h> 11 #include <asm/arch/clock.h> 12 #include <linux/ctype.h> 13 #ifdef CONFIG_FSL_ESDHC 14 #include <fsl_esdhc.h> 15 #endif 16 #include <tsec.h> 17 #include <asm/arch/immap_ls102xa.h> 18 #include <fsl_sec.h> 19 20 DECLARE_GLOBAL_DATA_PTR; 21 22 void ft_fixup_enet_phy_connect_type(void *fdt) 23 { 24 struct eth_device *dev; 25 struct tsec_private *priv; 26 const char *enet_path, *phy_path; 27 char enet[16]; 28 char phy[16]; 29 int phy_node; 30 int i = 0; 31 uint32_t ph; 32 char *name[3] = { "eTSEC1", "eTSEC2", "eTSEC3" }; 33 34 for (; i < ARRAY_SIZE(name); i++) { 35 dev = eth_get_dev_by_name(name[i]); 36 if (dev) { 37 sprintf(enet, "ethernet%d", i); 38 sprintf(phy, "enet%d_rgmii_phy", i); 39 } else { 40 continue; 41 } 42 43 priv = dev->priv; 44 if (priv->flags & TSEC_SGMII) 45 continue; 46 47 enet_path = fdt_get_alias(fdt, enet); 48 if (!enet_path) 49 continue; 50 51 phy_path = fdt_get_alias(fdt, phy); 52 if (!phy_path) 53 continue; 54 55 phy_node = fdt_path_offset(fdt, phy_path); 56 if (phy_node < 0) 57 continue; 58 59 ph = fdt_create_phandle(fdt, phy_node); 60 if (ph) 61 do_fixup_by_path_u32(fdt, enet_path, 62 "phy-handle", ph, 1); 63 64 do_fixup_by_path(fdt, enet_path, "phy-connection-type", 65 phy_string_for_interface( 66 PHY_INTERFACE_MODE_RGMII_ID), 67 sizeof(phy_string_for_interface( 68 PHY_INTERFACE_MODE_RGMII_ID)), 69 1); 70 } 71 } 72 73 void ft_cpu_setup(void *blob, bd_t *bd) 74 { 75 int off; 76 int val; 77 const char *sysclk_path; 78 struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR); 79 unsigned int svr; 80 svr = in_be32(&gur->svr); 81 82 unsigned long busclk = get_bus_freq(0); 83 84 /* delete crypto node if not on an E-processor */ 85 if (!IS_E_PROCESSOR(svr)) 86 fdt_fixup_crypto_node(blob, 0); 87 #if CONFIG_SYS_FSL_SEC_COMPAT >= 4 88 else { 89 ccsr_sec_t __iomem *sec; 90 91 sec = (void __iomem *)CONFIG_SYS_FSL_SEC_ADDR; 92 fdt_fixup_crypto_node(blob, sec_in32(&sec->secvid_ms)); 93 } 94 #endif 95 96 off = fdt_node_offset_by_prop_value(blob, -1, "device_type", "cpu", 4); 97 while (off != -FDT_ERR_NOTFOUND) { 98 val = gd->cpu_clk; 99 fdt_setprop(blob, off, "clock-frequency", &val, 4); 100 off = fdt_node_offset_by_prop_value(blob, off, 101 "device_type", "cpu", 4); 102 } 103 104 do_fixup_by_prop_u32(blob, "device_type", "soc", 105 4, "bus-frequency", busclk, 1); 106 107 ft_fixup_enet_phy_connect_type(blob); 108 109 #ifdef CONFIG_SYS_NS16550 110 do_fixup_by_compat_u32(blob, "fsl,16550-FIFO64", 111 "clock-frequency", CONFIG_SYS_NS16550_CLK, 1); 112 #endif 113 114 sysclk_path = fdt_get_alias(blob, "sysclk"); 115 if (sysclk_path) 116 do_fixup_by_path_u32(blob, sysclk_path, "clock-frequency", 117 CONFIG_SYS_CLK_FREQ, 1); 118 do_fixup_by_compat_u32(blob, "fsl,qoriq-sysclk-2.0", 119 "clock-frequency", CONFIG_SYS_CLK_FREQ, 1); 120 121 #if defined(CONFIG_DEEP_SLEEP) && defined(CONFIG_SD_BOOT) 122 #define UBOOT_HEAD_LEN 0x1000 123 /* 124 * Reserved memory in SD boot deep sleep case. 125 * Second stage uboot binary and malloc space should be reserved. 126 * If the memory they occupied has not been reserved, then this 127 * space would be used by kernel and overwritten in uboot when 128 * deep sleep resume, which cause deep sleep failed. 129 * Since second uboot binary has a head, that space need to be 130 * reserved either(assuming its size is less than 0x1000). 131 */ 132 off = fdt_add_mem_rsv(blob, CONFIG_SYS_TEXT_BASE - UBOOT_HEAD_LEN, 133 CONFIG_SYS_MONITOR_LEN + CONFIG_SYS_SPL_MALLOC_SIZE + 134 UBOOT_HEAD_LEN); 135 if (off < 0) 136 printf("Failed to reserve memory for SD boot deep sleep: %s\n", 137 fdt_strerror(off)); 138 #endif 139 140 #if defined(CONFIG_FSL_ESDHC) 141 fdt_fixup_esdhc(blob, bd); 142 #endif 143 144 /* 145 * platform bus clock = system bus clock/2 146 * Here busclk = system bus clock 147 * We are using the platform bus clock as 1588 Timer reference 148 * clock source select 149 */ 150 do_fixup_by_compat_u32(blob, "fsl, gianfar-ptp-timer", 151 "timer-frequency", busclk / 2, 1); 152 153 /* 154 * clock-freq should change to clock-frequency and 155 * flexcan-v1.0 should change to p1010-flexcan respectively 156 * in the future. 157 */ 158 do_fixup_by_compat_u32(blob, "fsl, flexcan-v1.0", 159 "clock_freq", busclk / 2, 1); 160 161 do_fixup_by_compat_u32(blob, "fsl, flexcan-v1.0", 162 "clock-frequency", busclk / 2, 1); 163 164 do_fixup_by_compat_u32(blob, "fsl, ls1021a-flexcan", 165 "clock-frequency", busclk / 2, 1); 166 167 #if defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI) 168 off = fdt_node_offset_by_compat_reg(blob, FSL_IFC_COMPAT, 169 CONFIG_SYS_IFC_ADDR); 170 fdt_set_node_status(blob, off, FDT_STATUS_DISABLED, 0); 171 #else 172 off = fdt_node_offset_by_compat_reg(blob, FSL_QSPI_COMPAT, 173 QSPI0_BASE_ADDR); 174 fdt_set_node_status(blob, off, FDT_STATUS_DISABLED, 0); 175 off = fdt_node_offset_by_compat_reg(blob, FSL_DSPI_COMPAT, 176 DSPI1_BASE_ADDR); 177 fdt_set_node_status(blob, off, FDT_STATUS_DISABLED, 0); 178 #endif 179 } 180