1 /* 2 * Copyright 2014 Freescale Semiconductor, Inc. 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 #include <common.h> 8 #include <asm/arch/clock.h> 9 #include <asm/io.h> 10 #include <asm/arch/immap_ls102xa.h> 11 #include <tsec.h> 12 #include <netdev.h> 13 #include <fsl_esdhc.h> 14 15 DECLARE_GLOBAL_DATA_PTR; 16 17 #if defined(CONFIG_DISPLAY_CPUINFO) 18 int print_cpuinfo(void) 19 { 20 char buf1[32], buf2[32]; 21 struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR); 22 unsigned int svr, major, minor, ver, i; 23 24 svr = in_be32(&gur->svr); 25 major = SVR_MAJ(svr); 26 minor = SVR_MIN(svr); 27 28 puts("CPU: Freescale LayerScape "); 29 30 ver = SVR_SOC_VER(svr); 31 switch (ver) { 32 case SOC_VER_SLS1020: 33 puts("SLS1020"); 34 break; 35 case SOC_VER_LS1020: 36 puts("LS1020"); 37 break; 38 case SOC_VER_LS1021: 39 puts("LS1021"); 40 break; 41 case SOC_VER_LS1022: 42 puts("LS1022"); 43 break; 44 default: 45 puts("Unknown"); 46 break; 47 } 48 49 if (IS_E_PROCESSOR(svr) && (ver != SOC_VER_SLS1020)) 50 puts("E"); 51 52 printf(", Version: %d.%d, (0x%08x)\n", major, minor, svr); 53 54 puts("Clock Configuration:"); 55 56 printf("\n CPU0(ARMV7):%-4s MHz, ", strmhz(buf1, gd->cpu_clk)); 57 printf("\n Bus:%-4s MHz, ", strmhz(buf1, gd->bus_clk)); 58 printf("DDR:%-4s MHz (%s MT/s data rate), ", 59 strmhz(buf1, gd->mem_clk/2), strmhz(buf2, gd->mem_clk)); 60 puts("\n"); 61 62 /* Display the RCW, so that no one gets confused as to what RCW 63 * we're actually using for this boot. 64 */ 65 puts("Reset Configuration Word (RCW):"); 66 for (i = 0; i < ARRAY_SIZE(gur->rcwsr); i++) { 67 u32 rcw = in_be32(&gur->rcwsr[i]); 68 69 if ((i % 4) == 0) 70 printf("\n %08x:", i * 4); 71 printf(" %08x", rcw); 72 } 73 puts("\n"); 74 75 return 0; 76 } 77 #endif 78 79 void enable_caches(void) 80 { 81 #ifndef CONFIG_SYS_ICACHE_OFF 82 icache_enable(); 83 #endif 84 #ifndef CONFIG_SYS_DCACHE_OFF 85 dcache_enable(); 86 #endif 87 } 88 89 #ifdef CONFIG_FSL_ESDHC 90 int cpu_mmc_init(bd_t *bis) 91 { 92 return fsl_esdhc_mmc_init(bis); 93 } 94 #endif 95 96 int cpu_eth_init(bd_t *bis) 97 { 98 #ifdef CONFIG_TSEC_ENET 99 tsec_standard_init(bis); 100 #endif 101 102 return 0; 103 } 104