1 /* 2 * Copyright 2014 Freescale Semiconductor, Inc. 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 #include <common.h> 8 #include <asm/arch/clock.h> 9 #include <asm/io.h> 10 #include <asm/arch/immap_ls102xa.h> 11 #include <asm/cache.h> 12 #include <asm/system.h> 13 #include <tsec.h> 14 #include <netdev.h> 15 #include <fsl_esdhc.h> 16 #include <config.h> 17 #include <fsl_wdog.h> 18 19 #include "fsl_epu.h" 20 21 #define DCSR_RCPM2_BLOCK_OFFSET 0x223000 22 #define DCSR_RCPM2_CPMFSMCR0 0x400 23 #define DCSR_RCPM2_CPMFSMSR0 0x404 24 #define DCSR_RCPM2_CPMFSMCR1 0x414 25 #define DCSR_RCPM2_CPMFSMSR1 0x418 26 #define CPMFSMSR_FSM_STATE_MASK 0x7f 27 28 DECLARE_GLOBAL_DATA_PTR; 29 30 #ifndef CONFIG_SYS_DCACHE_OFF 31 32 /* 33 * Bit[1] of the descriptor indicates the descriptor type, 34 * and bit[0] indicates whether the descriptor is valid. 35 */ 36 #define PMD_TYPE_TABLE 0x3 37 #define PMD_TYPE_SECT 0x1 38 39 /* AttrIndx[2:0] */ 40 #define PMD_ATTRINDX(t) ((t) << 2) 41 42 /* Section */ 43 #define PMD_SECT_AF (1 << 10) 44 45 #define BLOCK_SIZE_L1 (1UL << 30) 46 #define BLOCK_SIZE_L2 (1UL << 21) 47 48 /* TTBCR flags */ 49 #define TTBCR_EAE (1 << 31) 50 #define TTBCR_T0SZ(x) ((x) << 0) 51 #define TTBCR_T1SZ(x) ((x) << 16) 52 #define TTBCR_USING_TTBR0 (TTBCR_T0SZ(0) | TTBCR_T1SZ(0)) 53 #define TTBCR_IRGN0_NC (0 << 8) 54 #define TTBCR_IRGN0_WBWA (1 << 8) 55 #define TTBCR_IRGN0_WT (2 << 8) 56 #define TTBCR_IRGN0_WBNWA (3 << 8) 57 #define TTBCR_IRGN0_MASK (3 << 8) 58 #define TTBCR_ORGN0_NC (0 << 10) 59 #define TTBCR_ORGN0_WBWA (1 << 10) 60 #define TTBCR_ORGN0_WT (2 << 10) 61 #define TTBCR_ORGN0_WBNWA (3 << 10) 62 #define TTBCR_ORGN0_MASK (3 << 10) 63 #define TTBCR_SHARED_NON (0 << 12) 64 #define TTBCR_SHARED_OUTER (2 << 12) 65 #define TTBCR_SHARED_INNER (3 << 12) 66 #define TTBCR_EPD0 (0 << 7) 67 #define TTBCR (TTBCR_SHARED_NON | \ 68 TTBCR_ORGN0_NC | \ 69 TTBCR_IRGN0_NC | \ 70 TTBCR_USING_TTBR0 | \ 71 TTBCR_EAE) 72 73 /* 74 * Memory region attributes for LPAE (defined in pgtable): 75 * 76 * n = AttrIndx[2:0] 77 * 78 * n MAIR 79 * UNCACHED 000 00000000 80 * BUFFERABLE 001 01000100 81 * DEV_WC 001 01000100 82 * WRITETHROUGH 010 10101010 83 * WRITEBACK 011 11101110 84 * DEV_CACHED 011 11101110 85 * DEV_SHARED 100 00000100 86 * DEV_NONSHARED 100 00000100 87 * unused 101 88 * unused 110 89 * WRITEALLOC 111 11111111 90 */ 91 #define MT_MAIR0 0xeeaa4400 92 #define MT_MAIR1 0xff000004 93 #define MT_STRONLY_ORDER 0 94 #define MT_NORMAL_NC 1 95 #define MT_DEVICE_MEM 4 96 #define MT_NORMAL 7 97 98 /* The phy_addr must be aligned to 4KB */ 99 static inline void set_pgtable(u32 *page_table, u32 index, u32 phy_addr) 100 { 101 u32 value = phy_addr | PMD_TYPE_TABLE; 102 103 page_table[2 * index] = value; 104 page_table[2 * index + 1] = 0; 105 } 106 107 /* The phy_addr must be aligned to 4KB */ 108 static inline void set_pgsection(u32 *page_table, u32 index, u64 phy_addr, 109 u32 memory_type) 110 { 111 u64 value; 112 113 value = phy_addr | PMD_TYPE_SECT | PMD_SECT_AF; 114 value |= PMD_ATTRINDX(memory_type); 115 page_table[2 * index] = value & 0xFFFFFFFF; 116 page_table[2 * index + 1] = (value >> 32) & 0xFFFFFFFF; 117 } 118 119 /* 120 * Start MMU after DDR is available, we create MMU table in DRAM. 121 * The base address of TTLB is gd->arch.tlb_addr. We use two 122 * levels of translation tables here to cover 40-bit address space. 123 * 124 * The TTLBs are located at PHY 2G~4G. 125 * 126 * VA mapping: 127 * 128 * ------- <---- 0GB 129 * | | 130 * | | 131 * |-------| <---- 0x24000000 132 * |///////| ===> 192MB VA map for PCIe1 with offset 0x40_0000_0000 133 * |-------| <---- 0x300000000 134 * | | 135 * |-------| <---- 0x34000000 136 * |///////| ===> 192MB VA map for PCIe2 with offset 0x48_0000_0000 137 * |-------| <---- 0x40000000 138 * | | 139 * |-------| <---- 0x80000000 DDR0 space start 140 * |\\\\\\\| 141 *.|\\\\\\\| ===> 2GB VA map for 2GB DDR0 Memory space 142 * |\\\\\\\| 143 * ------- <---- 4GB DDR0 space end 144 */ 145 static void mmu_setup(void) 146 { 147 u32 *level0_table = (u32 *)gd->arch.tlb_addr; 148 u32 *level1_table = (u32 *)(gd->arch.tlb_addr + 0x1000); 149 u64 va_start = 0; 150 u32 reg; 151 int i; 152 153 /* Level 0 Table 2-3 are used to map DDR */ 154 set_pgsection(level0_table, 3, 3 * BLOCK_SIZE_L1, MT_NORMAL); 155 set_pgsection(level0_table, 2, 2 * BLOCK_SIZE_L1, MT_NORMAL); 156 /* Level 0 Table 1 is used to map device */ 157 set_pgsection(level0_table, 1, 1 * BLOCK_SIZE_L1, MT_DEVICE_MEM); 158 /* Level 0 Table 0 is used to map device including PCIe MEM */ 159 set_pgtable(level0_table, 0, (u32)level1_table); 160 161 /* Level 1 has 512 entries */ 162 for (i = 0; i < 512; i++) { 163 /* Mapping for PCIe 1 */ 164 if (va_start >= CONFIG_SYS_PCIE1_VIRT_ADDR && 165 va_start < (CONFIG_SYS_PCIE1_VIRT_ADDR + 166 CONFIG_SYS_PCIE_MMAP_SIZE)) 167 set_pgsection(level1_table, i, 168 CONFIG_SYS_PCIE1_PHYS_BASE + va_start, 169 MT_DEVICE_MEM); 170 /* Mapping for PCIe 2 */ 171 else if (va_start >= CONFIG_SYS_PCIE2_VIRT_ADDR && 172 va_start < (CONFIG_SYS_PCIE2_VIRT_ADDR + 173 CONFIG_SYS_PCIE_MMAP_SIZE)) 174 set_pgsection(level1_table, i, 175 CONFIG_SYS_PCIE2_PHYS_BASE + va_start, 176 MT_DEVICE_MEM); 177 else 178 set_pgsection(level1_table, i, 179 va_start, 180 MT_DEVICE_MEM); 181 va_start += BLOCK_SIZE_L2; 182 } 183 184 asm volatile("dsb sy;isb"); 185 asm volatile("mcr p15, 0, %0, c2, c0, 2" /* Write RT to TTBCR */ 186 : : "r" (TTBCR) : "memory"); 187 asm volatile("mcrr p15, 0, %0, %1, c2" /* TTBR 0 */ 188 : : "r" ((u32)level0_table), "r" (0) : "memory"); 189 asm volatile("mcr p15, 0, %0, c10, c2, 0" /* write MAIR 0 */ 190 : : "r" (MT_MAIR0) : "memory"); 191 asm volatile("mcr p15, 0, %0, c10, c2, 1" /* write MAIR 1 */ 192 : : "r" (MT_MAIR1) : "memory"); 193 194 /* Set the access control to all-supervisor */ 195 asm volatile("mcr p15, 0, %0, c3, c0, 0" 196 : : "r" (~0)); 197 198 /* Enable the mmu */ 199 reg = get_cr(); 200 set_cr(reg | CR_M); 201 } 202 203 /* 204 * This function is called from lib/board.c. It recreates MMU 205 * table in main memory. MMU and i/d-cache are enabled here. 206 */ 207 void enable_caches(void) 208 { 209 /* Invalidate all TLB */ 210 mmu_page_table_flush(gd->arch.tlb_addr, 211 gd->arch.tlb_addr + gd->arch.tlb_size); 212 /* Set up and enable mmu */ 213 mmu_setup(); 214 215 /* Invalidate & Enable d-cache */ 216 invalidate_dcache_all(); 217 set_cr(get_cr() | CR_C); 218 } 219 #endif /* #ifndef CONFIG_SYS_DCACHE_OFF */ 220 221 222 uint get_svr(void) 223 { 224 struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR); 225 226 return in_be32(&gur->svr); 227 } 228 229 #if defined(CONFIG_DISPLAY_CPUINFO) 230 int print_cpuinfo(void) 231 { 232 char buf1[32], buf2[32]; 233 struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR); 234 unsigned int svr, major, minor, ver, i; 235 236 svr = in_be32(&gur->svr); 237 major = SVR_MAJ(svr); 238 minor = SVR_MIN(svr); 239 240 puts("CPU: Freescale LayerScape "); 241 242 ver = SVR_SOC_VER(svr); 243 switch (ver) { 244 case SOC_VER_SLS1020: 245 puts("SLS1020"); 246 break; 247 case SOC_VER_LS1020: 248 puts("LS1020"); 249 break; 250 case SOC_VER_LS1021: 251 puts("LS1021"); 252 break; 253 case SOC_VER_LS1022: 254 puts("LS1022"); 255 break; 256 default: 257 puts("Unknown"); 258 break; 259 } 260 261 if (IS_E_PROCESSOR(svr) && (ver != SOC_VER_SLS1020)) 262 puts("E"); 263 264 printf(", Version: %d.%d, (0x%08x)\n", major, minor, svr); 265 266 puts("Clock Configuration:"); 267 268 printf("\n CPU0(ARMV7):%-4s MHz, ", strmhz(buf1, gd->cpu_clk)); 269 printf("\n Bus:%-4s MHz, ", strmhz(buf1, gd->bus_clk)); 270 printf("DDR:%-4s MHz (%s MT/s data rate), ", 271 strmhz(buf1, gd->mem_clk/2), strmhz(buf2, gd->mem_clk)); 272 puts("\n"); 273 274 /* Display the RCW, so that no one gets confused as to what RCW 275 * we're actually using for this boot. 276 */ 277 puts("Reset Configuration Word (RCW):"); 278 for (i = 0; i < ARRAY_SIZE(gur->rcwsr); i++) { 279 u32 rcw = in_be32(&gur->rcwsr[i]); 280 281 if ((i % 4) == 0) 282 printf("\n %08x:", i * 4); 283 printf(" %08x", rcw); 284 } 285 puts("\n"); 286 287 return 0; 288 } 289 #endif 290 291 #ifdef CONFIG_FSL_ESDHC 292 int cpu_mmc_init(bd_t *bis) 293 { 294 return fsl_esdhc_mmc_init(bis); 295 } 296 #endif 297 298 int cpu_eth_init(bd_t *bis) 299 { 300 #ifdef CONFIG_TSEC_ENET 301 tsec_standard_init(bis); 302 #endif 303 304 return 0; 305 } 306 307 int arch_cpu_init(void) 308 { 309 void *epu_base = (void *)(CONFIG_SYS_DCSRBAR + EPU_BLOCK_OFFSET); 310 void *rcpm2_base = 311 (void *)(CONFIG_SYS_DCSRBAR + DCSR_RCPM2_BLOCK_OFFSET); 312 struct ccsr_scfg *scfg = (void *)CONFIG_SYS_FSL_SCFG_ADDR; 313 u32 state; 314 315 /* 316 * The RCPM FSM state may not be reset after power-on. 317 * So, reset them. 318 */ 319 state = in_be32(rcpm2_base + DCSR_RCPM2_CPMFSMSR0) & 320 CPMFSMSR_FSM_STATE_MASK; 321 if (state != 0) { 322 out_be32(rcpm2_base + DCSR_RCPM2_CPMFSMCR0, 0x80); 323 out_be32(rcpm2_base + DCSR_RCPM2_CPMFSMCR0, 0x0); 324 } 325 326 state = in_be32(rcpm2_base + DCSR_RCPM2_CPMFSMSR1) & 327 CPMFSMSR_FSM_STATE_MASK; 328 if (state != 0) { 329 out_be32(rcpm2_base + DCSR_RCPM2_CPMFSMCR1, 0x80); 330 out_be32(rcpm2_base + DCSR_RCPM2_CPMFSMCR1, 0x0); 331 } 332 333 /* 334 * After wakeup from deep sleep, Clear EPU registers 335 * as early as possible to prevent from possible issue. 336 * It's also safe to clear at normal boot. 337 */ 338 fsl_epu_clean(epu_base); 339 340 setbits_be32(&scfg->snpcnfgcr, SCFG_SNPCNFGCR_SEC_RD_WR); 341 342 return 0; 343 } 344 345 #ifdef CONFIG_ARMV7_NONSEC 346 /* Set the address at which the secondary core starts from.*/ 347 void smp_set_core_boot_addr(unsigned long addr, int corenr) 348 { 349 struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR); 350 351 out_be32(&gur->scratchrw[0], addr); 352 } 353 354 /* Release the secondary core from holdoff state and kick it */ 355 void smp_kick_all_cpus(void) 356 { 357 struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR); 358 359 out_be32(&gur->brrl, 0x2); 360 361 /* 362 * LS1 STANDBYWFE is not captured outside the ARM module in the soc. 363 * So add a delay to wait bootrom execute WFE. 364 */ 365 udelay(1); 366 367 asm volatile("sev"); 368 } 369 #endif 370 371 void reset_cpu(ulong addr) 372 { 373 struct watchdog_regs *wdog = (struct watchdog_regs *)WDOG1_BASE_ADDR; 374 375 clrbits_be16(&wdog->wcr, WCR_SRS); 376 377 while (1) { 378 /* 379 * Let the watchdog trigger 380 */ 381 } 382 } 383 384 void arch_preboot_os(void) 385 { 386 unsigned long ctrl; 387 388 /* Disable PL1 Physical Timer */ 389 asm("mrc p15, 0, %0, c14, c2, 1" : "=r" (ctrl)); 390 ctrl &= ~ARCH_TIMER_CTRL_ENABLE; 391 asm("mcr p15, 0, %0, c14, c2, 1" : : "r" (ctrl)); 392 } 393