1config ARCH_LS1021A 2 bool 3 select SYS_FSL_ERRATUM_A008378 4 select SYS_FSL_ERRATUM_A008407 5 select SYS_FSL_ERRATUM_A009663 6 select SYS_FSL_ERRATUM_A009942 7 select SYS_FSL_ERRATUM_A010315 8 select SYS_FSL_SRDS_1 9 select SYS_HAS_SERDES 10 select SYS_FSL_DDR_BE if SYS_FSL_DDR 11 select SYS_FSL_DDR_VER_50 if SYS_FSL_DDR 12 select SYS_FSL_HAS_DDR3 if SYS_FSL_DDR 13 select SYS_FSL_HAS_DDR4 if SYS_FSL_DDR 14 select SYS_FSL_HAS_SEC 15 select SYS_FSL_SEC_COMPAT_5 16 select SYS_FSL_SEC_LE 17 imply SCSI 18 imply CMD_PCI 19 20menu "LS102xA architecture" 21 depends on ARCH_LS1021A 22 23config FSL_PCIE_COMPAT 24 string "PCIe compatible of Kernel DT" 25 depends on PCIE_LAYERSCAPE 26 default "fsl,ls1021a-pcie" if ARCH_LS1021A 27 help 28 This compatible is used to find pci controller node in Kernel DT 29 to complete fixup. 30 31config LS1_DEEP_SLEEP 32 bool "Deep sleep" 33 depends on ARCH_LS1021A 34 35config MAX_CPUS 36 int "Maximum number of CPUs permitted for LS102xA" 37 depends on ARCH_LS1021A 38 default 2 39 help 40 Set this number to the maximum number of possible CPUs in the SoC. 41 SoCs may have multiple clusters with each cluster may have multiple 42 ports. If some ports are reserved but higher ports are used for 43 cores, count the reserved ports. This will allocate enough memory 44 in spin table to properly handle all cores. 45 46config SECURE_BOOT 47 bool "Secure Boot" 48 help 49 Enable Freescale Secure Boot feature. Normally selected 50 by defconfig. If unsure, do not change. 51 52config SYS_FSL_ERRATUM_A010315 53 bool "Workaround for PCIe erratum A010315" 54 55config SYS_FSL_SRDS_1 56 bool 57 58config SYS_FSL_SRDS_2 59 bool 60 61config SYS_HAS_SERDES 62 bool 63 64config SYS_FSL_IFC_BANK_COUNT 65 int "Maximum banks of Integrated flash controller" 66 depends on ARCH_LS1021A 67 default 8 68 69config SYS_FSL_ERRATUM_A008407 70 bool 71 72endmenu 73