xref: /openbmc/u-boot/arch/arm/cpu/armv7/bcm281xx/reset.c (revision d66ff4ba)
1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3  * Copyright 2013 Broadcom Corporation.
4  */
5 
6 #include <common.h>
7 #include <asm/io.h>
8 #include <asm/arch/sysmap.h>
9 
10 #define EN_MASK		0x08000000	/* Enable timer */
11 #define SRSTEN_MASK	0x04000000	/* Enable soft reset */
12 #define CLKS_SHIFT	20		/* Clock period shift */
13 #define LD_SHIFT	0		/* Reload value shift */
14 
15 void reset_cpu(ulong ignored)
16 {
17 	/*
18 	 * Set WD enable, RST enable,
19 	 * 3.9 msec clock period (8), reload value (8*3.9ms)
20 	 */
21 	u32 reg = EN_MASK + SRSTEN_MASK + (8 << CLKS_SHIFT) + (8 << LD_SHIFT);
22 	writel(reg, SECWD2_BASE_ADDR);
23 
24 	while (1)
25 		;	/* loop forever till reset */
26 }
27