xref: /openbmc/u-boot/arch/arm/cpu/armv7/bcm281xx/reset.c (revision 20c700f8)
1 /*
2  * Copyright 2013 Broadcom Corporation.
3  *
4  * SPDX-License-Identifier:      GPL-2.0+
5  */
6 
7 #include <common.h>
8 #include <asm/io.h>
9 #include <asm/arch/sysmap.h>
10 
11 #define EN_MASK		0x08000000	/* Enable timer */
12 #define SRSTEN_MASK	0x04000000	/* Enable soft reset */
13 #define CLKS_SHIFT	20		/* Clock period shift */
14 #define LD_SHIFT	0		/* Reload value shift */
15 
16 void reset_cpu(ulong ignored)
17 {
18 	/*
19 	 * Set WD enable, RST enable,
20 	 * 3.9 msec clock period (8), reload value (8*3.9ms)
21 	 */
22 	u32 reg = EN_MASK + SRSTEN_MASK + (8 << CLKS_SHIFT) + (8 << LD_SHIFT);
23 	writel(reg, SECWD2_BASE_ADDR);
24 
25 	while (1)
26 		;	/* loop forever till reset */
27 }
28