1 /* 2 * Copyright 2013 Broadcom Corporation. 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 /* 8 * 9 * bcm281xx-specific clock tables 10 * 11 */ 12 13 #include <common.h> 14 #include <asm/io.h> 15 #include <asm/errno.h> 16 #include <asm/arch/sysmap.h> 17 #include <asm/kona-common/clk.h> 18 #include "clk-core.h" 19 20 #define CLOCK_1K 1000 21 #define CLOCK_1M (CLOCK_1K * 1000) 22 23 /* declare a reference clock */ 24 #define DECLARE_REF_CLK(clk_name, clk_parent, clk_rate, clk_div) \ 25 static struct refclk clk_name = { \ 26 .clk = { \ 27 .name = #clk_name, \ 28 .parent = clk_parent, \ 29 .rate = clk_rate, \ 30 .div = clk_div, \ 31 .ops = &ref_clk_ops, \ 32 }, \ 33 } 34 35 /* 36 * Reference clocks 37 */ 38 39 /* Declare a list of reference clocks */ 40 DECLARE_REF_CLK(ref_crystal, 0, 26 * CLOCK_1M, 1); 41 DECLARE_REF_CLK(var_96m, 0, 96 * CLOCK_1M, 1); 42 DECLARE_REF_CLK(ref_96m, 0, 96 * CLOCK_1M, 1); 43 DECLARE_REF_CLK(ref_312m, 0, 312 * CLOCK_1M, 0); 44 DECLARE_REF_CLK(ref_104m, &ref_312m.clk, 104 * CLOCK_1M, 3); 45 DECLARE_REF_CLK(ref_52m, &ref_104m.clk, 52 * CLOCK_1M, 2); 46 DECLARE_REF_CLK(ref_13m, &ref_52m.clk, 13 * CLOCK_1M, 4); 47 DECLARE_REF_CLK(var_312m, 0, 312 * CLOCK_1M, 0); 48 DECLARE_REF_CLK(var_104m, &var_312m.clk, 104 * CLOCK_1M, 3); 49 DECLARE_REF_CLK(var_52m, &var_104m.clk, 52 * CLOCK_1M, 2); 50 DECLARE_REF_CLK(var_13m, &var_52m.clk, 13 * CLOCK_1M, 4); 51 52 struct refclk_lkup { 53 struct refclk *procclk; 54 const char *name; 55 }; 56 57 /* Lookup table for string to clk tranlation */ 58 #define MKSTR(x) {&x, #x} 59 static struct refclk_lkup refclk_str_tbl[] = { 60 MKSTR(ref_crystal), MKSTR(var_96m), MKSTR(ref_96m), 61 MKSTR(ref_312m), MKSTR(ref_104m), MKSTR(ref_52m), 62 MKSTR(ref_13m), MKSTR(var_312m), MKSTR(var_104m), 63 MKSTR(var_52m), MKSTR(var_13m), 64 }; 65 66 int refclk_entries = sizeof(refclk_str_tbl)/sizeof(refclk_str_tbl[0]); 67 68 /* convert ref clock string to clock structure pointer */ 69 struct refclk *refclk_str_to_clk(const char *name) 70 { 71 int i; 72 struct refclk_lkup *tblp = refclk_str_tbl; 73 for (i = 0; i < refclk_entries; i++, tblp++) { 74 if (!(strcmp(name, tblp->name))) 75 return tblp->procclk; 76 } 77 return NULL; 78 } 79 80 /* frequency tables indexed by freq_id */ 81 unsigned long master_axi_freq_tbl[8] = { 82 26 * CLOCK_1M, 83 52 * CLOCK_1M, 84 104 * CLOCK_1M, 85 156 * CLOCK_1M, 86 156 * CLOCK_1M, 87 208 * CLOCK_1M, 88 312 * CLOCK_1M, 89 312 * CLOCK_1M 90 }; 91 92 unsigned long master_ahb_freq_tbl[8] = { 93 26 * CLOCK_1M, 94 52 * CLOCK_1M, 95 52 * CLOCK_1M, 96 52 * CLOCK_1M, 97 78 * CLOCK_1M, 98 104 * CLOCK_1M, 99 104 * CLOCK_1M, 100 156 * CLOCK_1M 101 }; 102 103 unsigned long slave_axi_freq_tbl[8] = { 104 26 * CLOCK_1M, 105 52 * CLOCK_1M, 106 78 * CLOCK_1M, 107 104 * CLOCK_1M, 108 156 * CLOCK_1M, 109 156 * CLOCK_1M 110 }; 111 112 unsigned long slave_apb_freq_tbl[8] = { 113 26 * CLOCK_1M, 114 26 * CLOCK_1M, 115 39 * CLOCK_1M, 116 52 * CLOCK_1M, 117 52 * CLOCK_1M, 118 78 * CLOCK_1M 119 }; 120 121 unsigned long esub_freq_tbl[8] = { 122 78 * CLOCK_1M, 123 156 * CLOCK_1M, 124 156 * CLOCK_1M, 125 156 * CLOCK_1M, 126 208 * CLOCK_1M, 127 208 * CLOCK_1M, 128 208 * CLOCK_1M 129 }; 130 131 static struct bus_clk_data bsc1_apb_data = { 132 .gate = HW_SW_GATE_AUTO(0x0458, 16, 0, 1), 133 }; 134 135 static struct bus_clk_data bsc2_apb_data = { 136 .gate = HW_SW_GATE_AUTO(0x045c, 16, 0, 1), 137 }; 138 139 static struct bus_clk_data bsc3_apb_data = { 140 .gate = HW_SW_GATE_AUTO(0x0484, 16, 0, 1), 141 }; 142 143 /* * Master CCU clocks */ 144 static struct peri_clk_data sdio1_data = { 145 .gate = HW_SW_GATE(0x0358, 18, 2, 3), 146 .clocks = CLOCKS("ref_crystal", 147 "var_52m", 148 "ref_52m", 149 "var_96m", 150 "ref_96m"), 151 .sel = SELECTOR(0x0a28, 0, 3), 152 .div = DIVIDER(0x0a28, 4, 14), 153 .trig = TRIGGER(0x0afc, 9), 154 }; 155 156 static struct peri_clk_data sdio2_data = { 157 .gate = HW_SW_GATE(0x035c, 18, 2, 3), 158 .clocks = CLOCKS("ref_crystal", 159 "var_52m", 160 "ref_52m", 161 "var_96m", 162 "ref_96m"), 163 .sel = SELECTOR(0x0a2c, 0, 3), 164 .div = DIVIDER(0x0a2c, 4, 14), 165 .trig = TRIGGER(0x0afc, 10), 166 }; 167 168 static struct peri_clk_data sdio3_data = { 169 .gate = HW_SW_GATE(0x0364, 18, 2, 3), 170 .clocks = CLOCKS("ref_crystal", 171 "var_52m", 172 "ref_52m", 173 "var_96m", 174 "ref_96m"), 175 .sel = SELECTOR(0x0a34, 0, 3), 176 .div = DIVIDER(0x0a34, 4, 14), 177 .trig = TRIGGER(0x0afc, 12), 178 }; 179 180 static struct peri_clk_data sdio4_data = { 181 .gate = HW_SW_GATE(0x0360, 18, 2, 3), 182 .clocks = CLOCKS("ref_crystal", 183 "var_52m", 184 "ref_52m", 185 "var_96m", 186 "ref_96m"), 187 .sel = SELECTOR(0x0a30, 0, 3), 188 .div = DIVIDER(0x0a30, 4, 14), 189 .trig = TRIGGER(0x0afc, 11), 190 }; 191 192 static struct peri_clk_data sdio1_sleep_data = { 193 .clocks = CLOCKS("ref_32k"), 194 .gate = SW_ONLY_GATE(0x0358, 20, 4), 195 }; 196 197 static struct peri_clk_data sdio2_sleep_data = { 198 .clocks = CLOCKS("ref_32k"), 199 .gate = SW_ONLY_GATE(0x035c, 20, 4), 200 }; 201 202 static struct peri_clk_data sdio3_sleep_data = { 203 .clocks = CLOCKS("ref_32k"), 204 .gate = SW_ONLY_GATE(0x0364, 20, 4), 205 }; 206 207 static struct peri_clk_data sdio4_sleep_data = { 208 .clocks = CLOCKS("ref_32k"), 209 .gate = SW_ONLY_GATE(0x0360, 20, 4), 210 }; 211 212 static struct bus_clk_data sdio1_ahb_data = { 213 .gate = HW_SW_GATE_AUTO(0x0358, 16, 0, 1), 214 }; 215 216 static struct bus_clk_data sdio2_ahb_data = { 217 .gate = HW_SW_GATE_AUTO(0x035c, 16, 0, 1), 218 }; 219 220 static struct bus_clk_data sdio3_ahb_data = { 221 .gate = HW_SW_GATE_AUTO(0x0364, 16, 0, 1), 222 }; 223 224 static struct bus_clk_data sdio4_ahb_data = { 225 .gate = HW_SW_GATE_AUTO(0x0360, 16, 0, 1), 226 }; 227 228 /* * Slave CCU clocks */ 229 static struct peri_clk_data bsc1_data = { 230 .gate = HW_SW_GATE(0x0458, 18, 2, 3), 231 .clocks = CLOCKS("ref_crystal", 232 "var_104m", 233 "ref_104m", 234 "var_13m", 235 "ref_13m"), 236 .sel = SELECTOR(0x0a64, 0, 3), 237 .trig = TRIGGER(0x0afc, 23), 238 }; 239 240 static struct peri_clk_data bsc2_data = { 241 .gate = HW_SW_GATE(0x045c, 18, 2, 3), 242 .clocks = CLOCKS("ref_crystal", 243 "var_104m", 244 "ref_104m", 245 "var_13m", 246 "ref_13m"), 247 .sel = SELECTOR(0x0a68, 0, 3), 248 .trig = TRIGGER(0x0afc, 24), 249 }; 250 251 static struct peri_clk_data bsc3_data = { 252 .gate = HW_SW_GATE(0x0484, 18, 2, 3), 253 .clocks = CLOCKS("ref_crystal", 254 "var_104m", 255 "ref_104m", 256 "var_13m", 257 "ref_13m"), 258 .sel = SELECTOR(0x0a84, 0, 3), 259 .trig = TRIGGER(0x0b00, 2), 260 }; 261 262 /* 263 * CCU clocks 264 */ 265 266 static struct ccu_clock kpm_ccu_clk = { 267 .clk = { 268 .name = "kpm_ccu_clk", 269 .ops = &ccu_clk_ops, 270 .ccu_clk_mgr_base = KONA_MST_CLK_BASE_ADDR, 271 }, 272 .num_policy_masks = 1, 273 .policy_freq_offset = 0x00000008, 274 .freq_bit_shift = 8, 275 .policy_ctl_offset = 0x0000000c, 276 .policy0_mask_offset = 0x00000010, 277 .policy1_mask_offset = 0x00000014, 278 .policy2_mask_offset = 0x00000018, 279 .policy3_mask_offset = 0x0000001c, 280 .lvm_en_offset = 0x00000034, 281 .freq_id = 2, 282 .freq_tbl = master_axi_freq_tbl, 283 }; 284 285 static struct ccu_clock kps_ccu_clk = { 286 .clk = { 287 .name = "kps_ccu_clk", 288 .ops = &ccu_clk_ops, 289 .ccu_clk_mgr_base = KONA_SLV_CLK_BASE_ADDR, 290 }, 291 .num_policy_masks = 2, 292 .policy_freq_offset = 0x00000008, 293 .freq_bit_shift = 8, 294 .policy_ctl_offset = 0x0000000c, 295 .policy0_mask_offset = 0x00000010, 296 .policy1_mask_offset = 0x00000014, 297 .policy2_mask_offset = 0x00000018, 298 .policy3_mask_offset = 0x0000001c, 299 .policy0_mask2_offset = 0x00000048, 300 .policy1_mask2_offset = 0x0000004c, 301 .policy2_mask2_offset = 0x00000050, 302 .policy3_mask2_offset = 0x00000054, 303 .lvm_en_offset = 0x00000034, 304 .freq_id = 2, 305 .freq_tbl = slave_axi_freq_tbl, 306 }; 307 308 #ifdef CONFIG_BCM_SF2_ETH 309 static struct ccu_clock esub_ccu_clk = { 310 .clk = { 311 .name = "esub_ccu_clk", 312 .ops = &ccu_clk_ops, 313 .ccu_clk_mgr_base = ESUB_CLK_BASE_ADDR, 314 }, 315 .num_policy_masks = 1, 316 .policy_freq_offset = 0x00000008, 317 .freq_bit_shift = 8, 318 .policy_ctl_offset = 0x0000000c, 319 .policy0_mask_offset = 0x00000010, 320 .policy1_mask_offset = 0x00000014, 321 .policy2_mask_offset = 0x00000018, 322 .policy3_mask_offset = 0x0000001c, 323 .lvm_en_offset = 0x00000034, 324 .freq_id = 2, 325 .freq_tbl = esub_freq_tbl, 326 }; 327 #endif 328 329 /* 330 * Bus clocks 331 */ 332 333 /* KPM bus clocks */ 334 static struct bus_clock sdio1_ahb_clk = { 335 .clk = { 336 .name = "sdio1_ahb_clk", 337 .parent = &kpm_ccu_clk.clk, 338 .ops = &bus_clk_ops, 339 .ccu_clk_mgr_base = KONA_MST_CLK_BASE_ADDR, 340 }, 341 .freq_tbl = master_ahb_freq_tbl, 342 .data = &sdio1_ahb_data, 343 }; 344 345 static struct bus_clock sdio2_ahb_clk = { 346 .clk = { 347 .name = "sdio2_ahb_clk", 348 .parent = &kpm_ccu_clk.clk, 349 .ops = &bus_clk_ops, 350 .ccu_clk_mgr_base = KONA_MST_CLK_BASE_ADDR, 351 }, 352 .freq_tbl = master_ahb_freq_tbl, 353 .data = &sdio2_ahb_data, 354 }; 355 356 static struct bus_clock sdio3_ahb_clk = { 357 .clk = { 358 .name = "sdio3_ahb_clk", 359 .parent = &kpm_ccu_clk.clk, 360 .ops = &bus_clk_ops, 361 .ccu_clk_mgr_base = KONA_MST_CLK_BASE_ADDR, 362 }, 363 .freq_tbl = master_ahb_freq_tbl, 364 .data = &sdio3_ahb_data, 365 }; 366 367 static struct bus_clock sdio4_ahb_clk = { 368 .clk = { 369 .name = "sdio4_ahb_clk", 370 .parent = &kpm_ccu_clk.clk, 371 .ops = &bus_clk_ops, 372 .ccu_clk_mgr_base = KONA_MST_CLK_BASE_ADDR, 373 }, 374 .freq_tbl = master_ahb_freq_tbl, 375 .data = &sdio4_ahb_data, 376 }; 377 378 static struct bus_clock bsc1_apb_clk = { 379 .clk = { 380 .name = "bsc1_apb_clk", 381 .parent = &kps_ccu_clk.clk, 382 .ops = &bus_clk_ops, 383 .ccu_clk_mgr_base = KONA_SLV_CLK_BASE_ADDR, 384 }, 385 .freq_tbl = slave_apb_freq_tbl, 386 .data = &bsc1_apb_data, 387 }; 388 389 static struct bus_clock bsc2_apb_clk = { 390 .clk = { 391 .name = "bsc2_apb_clk", 392 .parent = &kps_ccu_clk.clk, 393 .ops = &bus_clk_ops, 394 .ccu_clk_mgr_base = KONA_SLV_CLK_BASE_ADDR, 395 }, 396 .freq_tbl = slave_apb_freq_tbl, 397 .data = &bsc2_apb_data, 398 }; 399 400 static struct bus_clock bsc3_apb_clk = { 401 .clk = { 402 .name = "bsc3_apb_clk", 403 .parent = &kps_ccu_clk.clk, 404 .ops = &bus_clk_ops, 405 .ccu_clk_mgr_base = KONA_SLV_CLK_BASE_ADDR, 406 }, 407 .freq_tbl = slave_apb_freq_tbl, 408 .data = &bsc3_apb_data, 409 }; 410 411 /* KPM peripheral */ 412 static struct peri_clock sdio1_clk = { 413 .clk = { 414 .name = "sdio1_clk", 415 .parent = &ref_52m.clk, 416 .ops = &peri_clk_ops, 417 .ccu_clk_mgr_base = KONA_MST_CLK_BASE_ADDR, 418 }, 419 .data = &sdio1_data, 420 }; 421 422 static struct peri_clock sdio2_clk = { 423 .clk = { 424 .name = "sdio2_clk", 425 .parent = &ref_52m.clk, 426 .ops = &peri_clk_ops, 427 .ccu_clk_mgr_base = KONA_MST_CLK_BASE_ADDR, 428 }, 429 .data = &sdio2_data, 430 }; 431 432 static struct peri_clock sdio3_clk = { 433 .clk = { 434 .name = "sdio3_clk", 435 .parent = &ref_52m.clk, 436 .ops = &peri_clk_ops, 437 .ccu_clk_mgr_base = KONA_MST_CLK_BASE_ADDR, 438 }, 439 .data = &sdio3_data, 440 }; 441 442 static struct peri_clock sdio4_clk = { 443 .clk = { 444 .name = "sdio4_clk", 445 .parent = &ref_52m.clk, 446 .ops = &peri_clk_ops, 447 .ccu_clk_mgr_base = KONA_MST_CLK_BASE_ADDR, 448 }, 449 .data = &sdio4_data, 450 }; 451 452 static struct peri_clock sdio1_sleep_clk = { 453 .clk = { 454 .name = "sdio1_sleep_clk", 455 .parent = &kpm_ccu_clk.clk, 456 .ops = &bus_clk_ops, 457 .ccu_clk_mgr_base = KONA_MST_CLK_BASE_ADDR, 458 }, 459 .data = &sdio1_sleep_data, 460 }; 461 462 static struct peri_clock sdio2_sleep_clk = { 463 .clk = { 464 .name = "sdio2_sleep_clk", 465 .parent = &kpm_ccu_clk.clk, 466 .ops = &bus_clk_ops, 467 .ccu_clk_mgr_base = KONA_MST_CLK_BASE_ADDR, 468 }, 469 .data = &sdio2_sleep_data, 470 }; 471 472 static struct peri_clock sdio3_sleep_clk = { 473 .clk = { 474 .name = "sdio3_sleep_clk", 475 .parent = &kpm_ccu_clk.clk, 476 .ops = &bus_clk_ops, 477 .ccu_clk_mgr_base = KONA_MST_CLK_BASE_ADDR, 478 }, 479 .data = &sdio3_sleep_data, 480 }; 481 482 static struct peri_clock sdio4_sleep_clk = { 483 .clk = { 484 .name = "sdio4_sleep_clk", 485 .parent = &kpm_ccu_clk.clk, 486 .ops = &bus_clk_ops, 487 .ccu_clk_mgr_base = KONA_MST_CLK_BASE_ADDR, 488 }, 489 .data = &sdio4_sleep_data, 490 }; 491 492 /* KPS peripheral clock */ 493 static struct peri_clock bsc1_clk = { 494 .clk = { 495 .name = "bsc1_clk", 496 .parent = &ref_13m.clk, 497 .rate = 13 * CLOCK_1M, 498 .div = 1, 499 .ops = &peri_clk_ops, 500 .ccu_clk_mgr_base = KONA_SLV_CLK_BASE_ADDR, 501 }, 502 .data = &bsc1_data, 503 }; 504 505 static struct peri_clock bsc2_clk = { 506 .clk = { 507 .name = "bsc2_clk", 508 .parent = &ref_13m.clk, 509 .rate = 13 * CLOCK_1M, 510 .div = 1, 511 .ops = &peri_clk_ops, 512 .ccu_clk_mgr_base = KONA_SLV_CLK_BASE_ADDR, 513 }, 514 .data = &bsc2_data, 515 }; 516 517 static struct peri_clock bsc3_clk = { 518 .clk = { 519 .name = "bsc3_clk", 520 .parent = &ref_13m.clk, 521 .rate = 13 * CLOCK_1M, 522 .div = 1, 523 .ops = &peri_clk_ops, 524 .ccu_clk_mgr_base = KONA_SLV_CLK_BASE_ADDR, 525 }, 526 .data = &bsc3_data, 527 }; 528 529 /* public table for registering clocks */ 530 struct clk_lookup arch_clk_tbl[] = { 531 /* Peripheral clocks */ 532 CLK_LK(sdio1), 533 CLK_LK(sdio2), 534 CLK_LK(sdio3), 535 CLK_LK(sdio4), 536 CLK_LK(sdio1_sleep), 537 CLK_LK(sdio2_sleep), 538 CLK_LK(sdio3_sleep), 539 CLK_LK(sdio4_sleep), 540 CLK_LK(bsc1), 541 CLK_LK(bsc2), 542 CLK_LK(bsc3), 543 /* Bus clocks */ 544 CLK_LK(sdio1_ahb), 545 CLK_LK(sdio2_ahb), 546 CLK_LK(sdio3_ahb), 547 CLK_LK(sdio4_ahb), 548 CLK_LK(bsc1_apb), 549 CLK_LK(bsc2_apb), 550 CLK_LK(bsc3_apb), 551 #ifdef CONFIG_BCM_SF2_ETH 552 CLK_LK(esub_ccu), 553 #endif 554 }; 555 556 /* public array size */ 557 unsigned int arch_clk_tbl_array_size = ARRAY_SIZE(arch_clk_tbl); 558