1 /* 2 * Copyright 2013 Broadcom Corporation. 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 /* 8 * 9 * bcm235xx-specific clock tables 10 * 11 */ 12 13 #include <common.h> 14 #include <asm/io.h> 15 #include <linux/errno.h> 16 #include <asm/arch/sysmap.h> 17 #include <asm/kona-common/clk.h> 18 #include "clk-core.h" 19 20 #define CLOCK_1K 1000 21 #define CLOCK_1M (CLOCK_1K * 1000) 22 23 /* declare a reference clock */ 24 #define DECLARE_REF_CLK(clk_name, clk_parent, clk_rate, clk_div) \ 25 static struct refclk clk_name = { \ 26 .clk = { \ 27 .name = #clk_name, \ 28 .parent = clk_parent, \ 29 .rate = clk_rate, \ 30 .div = clk_div, \ 31 .ops = &ref_clk_ops, \ 32 }, \ 33 } 34 35 /* 36 * Reference clocks 37 */ 38 39 /* Declare a list of reference clocks */ 40 DECLARE_REF_CLK(ref_crystal, 0, 26 * CLOCK_1M, 1); 41 DECLARE_REF_CLK(var_96m, 0, 96 * CLOCK_1M, 1); 42 DECLARE_REF_CLK(ref_96m, 0, 96 * CLOCK_1M, 1); 43 DECLARE_REF_CLK(ref_312m, 0, 312 * CLOCK_1M, 0); 44 DECLARE_REF_CLK(ref_104m, &ref_312m.clk, 104 * CLOCK_1M, 3); 45 DECLARE_REF_CLK(ref_52m, &ref_104m.clk, 52 * CLOCK_1M, 2); 46 DECLARE_REF_CLK(ref_13m, &ref_52m.clk, 13 * CLOCK_1M, 4); 47 DECLARE_REF_CLK(var_312m, 0, 312 * CLOCK_1M, 0); 48 DECLARE_REF_CLK(var_104m, &var_312m.clk, 104 * CLOCK_1M, 3); 49 DECLARE_REF_CLK(var_52m, &var_104m.clk, 52 * CLOCK_1M, 2); 50 DECLARE_REF_CLK(var_13m, &var_52m.clk, 13 * CLOCK_1M, 4); 51 52 struct refclk_lkup { 53 struct refclk *procclk; 54 const char *name; 55 }; 56 57 /* Lookup table for string to clk tranlation */ 58 #define MKSTR(x) {&x, #x} 59 static struct refclk_lkup refclk_str_tbl[] = { 60 MKSTR(ref_crystal), MKSTR(var_96m), MKSTR(ref_96m), 61 MKSTR(ref_312m), MKSTR(ref_104m), MKSTR(ref_52m), 62 MKSTR(ref_13m), MKSTR(var_312m), MKSTR(var_104m), 63 MKSTR(var_52m), MKSTR(var_13m), 64 }; 65 66 int refclk_entries = sizeof(refclk_str_tbl)/sizeof(refclk_str_tbl[0]); 67 68 /* convert ref clock string to clock structure pointer */ 69 struct refclk *refclk_str_to_clk(const char *name) 70 { 71 int i; 72 struct refclk_lkup *tblp = refclk_str_tbl; 73 for (i = 0; i < refclk_entries; i++, tblp++) { 74 if (!(strcmp(name, tblp->name))) 75 return tblp->procclk; 76 } 77 return NULL; 78 } 79 80 /* frequency tables indexed by freq_id */ 81 unsigned long master_axi_freq_tbl[8] = { 82 26 * CLOCK_1M, 83 52 * CLOCK_1M, 84 104 * CLOCK_1M, 85 156 * CLOCK_1M, 86 156 * CLOCK_1M, 87 208 * CLOCK_1M, 88 312 * CLOCK_1M, 89 312 * CLOCK_1M 90 }; 91 92 unsigned long master_ahb_freq_tbl[8] = { 93 26 * CLOCK_1M, 94 52 * CLOCK_1M, 95 52 * CLOCK_1M, 96 52 * CLOCK_1M, 97 78 * CLOCK_1M, 98 104 * CLOCK_1M, 99 104 * CLOCK_1M, 100 156 * CLOCK_1M 101 }; 102 103 unsigned long slave_axi_freq_tbl[8] = { 104 26 * CLOCK_1M, 105 52 * CLOCK_1M, 106 78 * CLOCK_1M, 107 104 * CLOCK_1M, 108 156 * CLOCK_1M, 109 156 * CLOCK_1M 110 }; 111 112 unsigned long slave_apb_freq_tbl[8] = { 113 26 * CLOCK_1M, 114 26 * CLOCK_1M, 115 39 * CLOCK_1M, 116 52 * CLOCK_1M, 117 52 * CLOCK_1M, 118 78 * CLOCK_1M 119 }; 120 121 unsigned long esub_freq_tbl[8] = { 122 78 * CLOCK_1M, 123 156 * CLOCK_1M, 124 156 * CLOCK_1M, 125 156 * CLOCK_1M, 126 208 * CLOCK_1M, 127 208 * CLOCK_1M, 128 208 * CLOCK_1M 129 }; 130 131 static struct bus_clk_data bsc1_apb_data = { 132 .gate = HW_SW_GATE_AUTO(0x0458, 16, 0, 1), 133 }; 134 135 static struct bus_clk_data bsc2_apb_data = { 136 .gate = HW_SW_GATE_AUTO(0x045c, 16, 0, 1), 137 }; 138 139 static struct bus_clk_data bsc3_apb_data = { 140 .gate = HW_SW_GATE_AUTO(0x0484, 16, 0, 1), 141 }; 142 143 /* * Master CCU clocks */ 144 static struct peri_clk_data sdio1_data = { 145 .gate = HW_SW_GATE(0x0358, 18, 2, 3), 146 .clocks = CLOCKS("ref_crystal", 147 "var_52m", 148 "ref_52m", 149 "var_96m", 150 "ref_96m"), 151 .sel = SELECTOR(0x0a28, 0, 3), 152 .div = DIVIDER(0x0a28, 4, 14), 153 .trig = TRIGGER(0x0afc, 9), 154 }; 155 156 static struct peri_clk_data sdio2_data = { 157 .gate = HW_SW_GATE(0x035c, 18, 2, 3), 158 .clocks = CLOCKS("ref_crystal", 159 "var_52m", 160 "ref_52m", 161 "var_96m", 162 "ref_96m"), 163 .sel = SELECTOR(0x0a2c, 0, 3), 164 .div = DIVIDER(0x0a2c, 4, 14), 165 .trig = TRIGGER(0x0afc, 10), 166 }; 167 168 static struct peri_clk_data sdio3_data = { 169 .gate = HW_SW_GATE(0x0364, 18, 2, 3), 170 .clocks = CLOCKS("ref_crystal", 171 "var_52m", 172 "ref_52m", 173 "var_96m", 174 "ref_96m"), 175 .sel = SELECTOR(0x0a34, 0, 3), 176 .div = DIVIDER(0x0a34, 4, 14), 177 .trig = TRIGGER(0x0afc, 12), 178 }; 179 180 static struct peri_clk_data sdio4_data = { 181 .gate = HW_SW_GATE(0x0360, 18, 2, 3), 182 .clocks = CLOCKS("ref_crystal", 183 "var_52m", 184 "ref_52m", 185 "var_96m", 186 "ref_96m"), 187 .sel = SELECTOR(0x0a30, 0, 3), 188 .div = DIVIDER(0x0a30, 4, 14), 189 .trig = TRIGGER(0x0afc, 11), 190 }; 191 192 static struct peri_clk_data sdio1_sleep_data = { 193 .clocks = CLOCKS("ref_32k"), 194 .gate = SW_ONLY_GATE(0x0358, 20, 4), 195 }; 196 197 static struct peri_clk_data sdio2_sleep_data = { 198 .clocks = CLOCKS("ref_32k"), 199 .gate = SW_ONLY_GATE(0x035c, 20, 4), 200 }; 201 202 static struct peri_clk_data sdio3_sleep_data = { 203 .clocks = CLOCKS("ref_32k"), 204 .gate = SW_ONLY_GATE(0x0364, 20, 4), 205 }; 206 207 static struct peri_clk_data sdio4_sleep_data = { 208 .clocks = CLOCKS("ref_32k"), 209 .gate = SW_ONLY_GATE(0x0360, 20, 4), 210 }; 211 212 static struct bus_clk_data usb_otg_ahb_data = { 213 .gate = HW_SW_GATE_AUTO(0x0348, 16, 0, 1), 214 }; 215 216 static struct bus_clk_data sdio1_ahb_data = { 217 .gate = HW_SW_GATE_AUTO(0x0358, 16, 0, 1), 218 }; 219 220 static struct bus_clk_data sdio2_ahb_data = { 221 .gate = HW_SW_GATE_AUTO(0x035c, 16, 0, 1), 222 }; 223 224 static struct bus_clk_data sdio3_ahb_data = { 225 .gate = HW_SW_GATE_AUTO(0x0364, 16, 0, 1), 226 }; 227 228 static struct bus_clk_data sdio4_ahb_data = { 229 .gate = HW_SW_GATE_AUTO(0x0360, 16, 0, 1), 230 }; 231 232 /* * Slave CCU clocks */ 233 static struct peri_clk_data bsc1_data = { 234 .gate = HW_SW_GATE(0x0458, 18, 2, 3), 235 .clocks = CLOCKS("ref_crystal", 236 "var_104m", 237 "ref_104m", 238 "var_13m", 239 "ref_13m"), 240 .sel = SELECTOR(0x0a64, 0, 3), 241 .trig = TRIGGER(0x0afc, 23), 242 }; 243 244 static struct peri_clk_data bsc2_data = { 245 .gate = HW_SW_GATE(0x045c, 18, 2, 3), 246 .clocks = CLOCKS("ref_crystal", 247 "var_104m", 248 "ref_104m", 249 "var_13m", 250 "ref_13m"), 251 .sel = SELECTOR(0x0a68, 0, 3), 252 .trig = TRIGGER(0x0afc, 24), 253 }; 254 255 static struct peri_clk_data bsc3_data = { 256 .gate = HW_SW_GATE(0x0484, 18, 2, 3), 257 .clocks = CLOCKS("ref_crystal", 258 "var_104m", 259 "ref_104m", 260 "var_13m", 261 "ref_13m"), 262 .sel = SELECTOR(0x0a84, 0, 3), 263 .trig = TRIGGER(0x0b00, 2), 264 }; 265 266 /* 267 * CCU clocks 268 */ 269 270 static struct ccu_clock kpm_ccu_clk = { 271 .clk = { 272 .name = "kpm_ccu_clk", 273 .ops = &ccu_clk_ops, 274 .ccu_clk_mgr_base = KONA_MST_CLK_BASE_ADDR, 275 }, 276 .num_policy_masks = 1, 277 .policy_freq_offset = 0x00000008, 278 .freq_bit_shift = 8, 279 .policy_ctl_offset = 0x0000000c, 280 .policy0_mask_offset = 0x00000010, 281 .policy1_mask_offset = 0x00000014, 282 .policy2_mask_offset = 0x00000018, 283 .policy3_mask_offset = 0x0000001c, 284 .lvm_en_offset = 0x00000034, 285 .freq_id = 2, 286 .freq_tbl = master_axi_freq_tbl, 287 }; 288 289 static struct ccu_clock kps_ccu_clk = { 290 .clk = { 291 .name = "kps_ccu_clk", 292 .ops = &ccu_clk_ops, 293 .ccu_clk_mgr_base = KONA_SLV_CLK_BASE_ADDR, 294 }, 295 .num_policy_masks = 1, 296 .policy_freq_offset = 0x00000008, 297 .freq_bit_shift = 8, 298 .policy_ctl_offset = 0x0000000c, 299 .policy0_mask_offset = 0x00000010, 300 .policy1_mask_offset = 0x00000014, 301 .policy2_mask_offset = 0x00000018, 302 .policy3_mask_offset = 0x0000001c, 303 .lvm_en_offset = 0x00000034, 304 .freq_id = 2, 305 .freq_tbl = slave_axi_freq_tbl, 306 }; 307 308 #ifdef CONFIG_BCM_SF2_ETH 309 static struct ccu_clock esub_ccu_clk = { 310 .clk = { 311 .name = "esub_ccu_clk", 312 .ops = &ccu_clk_ops, 313 .ccu_clk_mgr_base = ESUB_CLK_BASE_ADDR, 314 }, 315 .num_policy_masks = 1, 316 .policy_freq_offset = 0x00000008, 317 .freq_bit_shift = 8, 318 .policy_ctl_offset = 0x0000000c, 319 .policy0_mask_offset = 0x00000010, 320 .policy1_mask_offset = 0x00000014, 321 .policy2_mask_offset = 0x00000018, 322 .policy3_mask_offset = 0x0000001c, 323 .lvm_en_offset = 0x00000034, 324 .freq_id = 2, 325 .freq_tbl = esub_freq_tbl, 326 }; 327 #endif 328 329 /* 330 * Bus clocks 331 */ 332 333 /* KPM bus clocks */ 334 static struct bus_clock usb_otg_ahb_clk = { 335 .clk = { 336 .name = "usb_otg_ahb_clk", 337 .parent = &kpm_ccu_clk.clk, 338 .ops = &bus_clk_ops, 339 .ccu_clk_mgr_base = KONA_MST_CLK_BASE_ADDR, 340 }, 341 .freq_tbl = master_ahb_freq_tbl, 342 .data = &usb_otg_ahb_data, 343 }; 344 345 static struct bus_clock sdio1_ahb_clk = { 346 .clk = { 347 .name = "sdio1_ahb_clk", 348 .parent = &kpm_ccu_clk.clk, 349 .ops = &bus_clk_ops, 350 .ccu_clk_mgr_base = KONA_MST_CLK_BASE_ADDR, 351 }, 352 .freq_tbl = master_ahb_freq_tbl, 353 .data = &sdio1_ahb_data, 354 }; 355 356 static struct bus_clock sdio2_ahb_clk = { 357 .clk = { 358 .name = "sdio2_ahb_clk", 359 .parent = &kpm_ccu_clk.clk, 360 .ops = &bus_clk_ops, 361 .ccu_clk_mgr_base = KONA_MST_CLK_BASE_ADDR, 362 }, 363 .freq_tbl = master_ahb_freq_tbl, 364 .data = &sdio2_ahb_data, 365 }; 366 367 static struct bus_clock sdio3_ahb_clk = { 368 .clk = { 369 .name = "sdio3_ahb_clk", 370 .parent = &kpm_ccu_clk.clk, 371 .ops = &bus_clk_ops, 372 .ccu_clk_mgr_base = KONA_MST_CLK_BASE_ADDR, 373 }, 374 .freq_tbl = master_ahb_freq_tbl, 375 .data = &sdio3_ahb_data, 376 }; 377 378 static struct bus_clock sdio4_ahb_clk = { 379 .clk = { 380 .name = "sdio4_ahb_clk", 381 .parent = &kpm_ccu_clk.clk, 382 .ops = &bus_clk_ops, 383 .ccu_clk_mgr_base = KONA_MST_CLK_BASE_ADDR, 384 }, 385 .freq_tbl = master_ahb_freq_tbl, 386 .data = &sdio4_ahb_data, 387 }; 388 389 static struct bus_clock bsc1_apb_clk = { 390 .clk = { 391 .name = "bsc1_apb_clk", 392 .parent = &kps_ccu_clk.clk, 393 .ops = &bus_clk_ops, 394 .ccu_clk_mgr_base = KONA_SLV_CLK_BASE_ADDR, 395 }, 396 .freq_tbl = slave_apb_freq_tbl, 397 .data = &bsc1_apb_data, 398 }; 399 400 static struct bus_clock bsc2_apb_clk = { 401 .clk = { 402 .name = "bsc2_apb_clk", 403 .parent = &kps_ccu_clk.clk, 404 .ops = &bus_clk_ops, 405 .ccu_clk_mgr_base = KONA_SLV_CLK_BASE_ADDR, 406 }, 407 .freq_tbl = slave_apb_freq_tbl, 408 .data = &bsc2_apb_data, 409 }; 410 411 static struct bus_clock bsc3_apb_clk = { 412 .clk = { 413 .name = "bsc3_apb_clk", 414 .parent = &kps_ccu_clk.clk, 415 .ops = &bus_clk_ops, 416 .ccu_clk_mgr_base = KONA_SLV_CLK_BASE_ADDR, 417 }, 418 .freq_tbl = slave_apb_freq_tbl, 419 .data = &bsc3_apb_data, 420 }; 421 422 /* KPM peripheral */ 423 static struct peri_clock sdio1_clk = { 424 .clk = { 425 .name = "sdio1_clk", 426 .parent = &ref_52m.clk, 427 .ops = &peri_clk_ops, 428 .ccu_clk_mgr_base = KONA_MST_CLK_BASE_ADDR, 429 }, 430 .data = &sdio1_data, 431 }; 432 433 static struct peri_clock sdio2_clk = { 434 .clk = { 435 .name = "sdio2_clk", 436 .parent = &ref_52m.clk, 437 .ops = &peri_clk_ops, 438 .ccu_clk_mgr_base = KONA_MST_CLK_BASE_ADDR, 439 }, 440 .data = &sdio2_data, 441 }; 442 443 static struct peri_clock sdio3_clk = { 444 .clk = { 445 .name = "sdio3_clk", 446 .parent = &ref_52m.clk, 447 .ops = &peri_clk_ops, 448 .ccu_clk_mgr_base = KONA_MST_CLK_BASE_ADDR, 449 }, 450 .data = &sdio3_data, 451 }; 452 453 static struct peri_clock sdio4_clk = { 454 .clk = { 455 .name = "sdio4_clk", 456 .parent = &ref_52m.clk, 457 .ops = &peri_clk_ops, 458 .ccu_clk_mgr_base = KONA_MST_CLK_BASE_ADDR, 459 }, 460 .data = &sdio4_data, 461 }; 462 463 static struct peri_clock sdio1_sleep_clk = { 464 .clk = { 465 .name = "sdio1_sleep_clk", 466 .parent = &kpm_ccu_clk.clk, 467 .ops = &bus_clk_ops, 468 .ccu_clk_mgr_base = KONA_MST_CLK_BASE_ADDR, 469 }, 470 .data = &sdio1_sleep_data, 471 }; 472 473 static struct peri_clock sdio2_sleep_clk = { 474 .clk = { 475 .name = "sdio2_sleep_clk", 476 .parent = &kpm_ccu_clk.clk, 477 .ops = &bus_clk_ops, 478 .ccu_clk_mgr_base = KONA_MST_CLK_BASE_ADDR, 479 }, 480 .data = &sdio2_sleep_data, 481 }; 482 483 static struct peri_clock sdio3_sleep_clk = { 484 .clk = { 485 .name = "sdio3_sleep_clk", 486 .parent = &kpm_ccu_clk.clk, 487 .ops = &bus_clk_ops, 488 .ccu_clk_mgr_base = KONA_MST_CLK_BASE_ADDR, 489 }, 490 .data = &sdio3_sleep_data, 491 }; 492 493 static struct peri_clock sdio4_sleep_clk = { 494 .clk = { 495 .name = "sdio4_sleep_clk", 496 .parent = &kpm_ccu_clk.clk, 497 .ops = &bus_clk_ops, 498 .ccu_clk_mgr_base = KONA_MST_CLK_BASE_ADDR, 499 }, 500 .data = &sdio4_sleep_data, 501 }; 502 503 /* KPS peripheral clock */ 504 static struct peri_clock bsc1_clk = { 505 .clk = { 506 .name = "bsc1_clk", 507 .parent = &ref_13m.clk, 508 .rate = 13 * CLOCK_1M, 509 .div = 1, 510 .ops = &peri_clk_ops, 511 .ccu_clk_mgr_base = KONA_SLV_CLK_BASE_ADDR, 512 }, 513 .data = &bsc1_data, 514 }; 515 516 static struct peri_clock bsc2_clk = { 517 .clk = { 518 .name = "bsc2_clk", 519 .parent = &ref_13m.clk, 520 .rate = 13 * CLOCK_1M, 521 .div = 1, 522 .ops = &peri_clk_ops, 523 .ccu_clk_mgr_base = KONA_SLV_CLK_BASE_ADDR, 524 }, 525 .data = &bsc2_data, 526 }; 527 528 static struct peri_clock bsc3_clk = { 529 .clk = { 530 .name = "bsc3_clk", 531 .parent = &ref_13m.clk, 532 .rate = 13 * CLOCK_1M, 533 .div = 1, 534 .ops = &peri_clk_ops, 535 .ccu_clk_mgr_base = KONA_SLV_CLK_BASE_ADDR, 536 }, 537 .data = &bsc3_data, 538 }; 539 540 /* public table for registering clocks */ 541 struct clk_lookup arch_clk_tbl[] = { 542 /* Peripheral clocks */ 543 CLK_LK(sdio1), 544 CLK_LK(sdio2), 545 CLK_LK(sdio3), 546 CLK_LK(sdio4), 547 CLK_LK(sdio1_sleep), 548 CLK_LK(sdio2_sleep), 549 CLK_LK(sdio3_sleep), 550 CLK_LK(sdio4_sleep), 551 CLK_LK(bsc1), 552 CLK_LK(bsc2), 553 CLK_LK(bsc3), 554 /* Bus clocks */ 555 CLK_LK(usb_otg_ahb), 556 CLK_LK(sdio1_ahb), 557 CLK_LK(sdio2_ahb), 558 CLK_LK(sdio3_ahb), 559 CLK_LK(sdio4_ahb), 560 CLK_LK(bsc1_apb), 561 CLK_LK(bsc2_apb), 562 CLK_LK(bsc3_apb), 563 #ifdef CONFIG_BCM_SF2_ETH 564 CLK_LK(esub_ccu), 565 #endif 566 }; 567 568 /* public array size */ 569 unsigned int arch_clk_tbl_array_size = ARRAY_SIZE(arch_clk_tbl); 570