1/* 2 * armboot - Startup Code for ARM926EJS CPU-core 3 * 4 * Copyright (c) 2003 Texas Instruments 5 * 6 * ----- Adapted for OMAP1610 OMAP730 from ARM925t code ------ 7 * 8 * Copyright (c) 2001 Marius Gröger <mag@sysgo.de> 9 * Copyright (c) 2002 Alex Züpke <azu@sysgo.de> 10 * Copyright (c) 2002 Gary Jennejohn <garyj@denx.de> 11 * Copyright (c) 2003 Richard Woodruff <r-woodruff2@ti.com> 12 * Copyright (c) 2003 Kshitij <kshitij@ti.com> 13 * Copyright (c) 2010 Albert Aribaud <albert.u.boot@aribaud.net> 14 * 15 * SPDX-License-Identifier: GPL-2.0+ 16 */ 17 18#include <asm-offsets.h> 19#include <config.h> 20#include <version.h> 21 22/* 23 ************************************************************************* 24 * 25 * Startup Code (reset vector) 26 * 27 * do important init only if we don't start from memory! 28 * setup Memory and board specific bits prior to relocation. 29 * relocate armboot to ram 30 * setup stack 31 * 32 ************************************************************************* 33 */ 34 35 .globl reset 36 37reset: 38 /* 39 * set the cpu to SVC32 mode 40 */ 41 mrs r0,cpsr 42 bic r0,r0,#0x1f 43 orr r0,r0,#0xd3 44 msr cpsr,r0 45 46 /* 47 * we do sys-critical inits only at reboot, 48 * not when booting from ram! 49 */ 50#ifndef CONFIG_SKIP_LOWLEVEL_INIT 51 bl cpu_init_crit 52#endif 53 54 bl _main 55 56/*------------------------------------------------------------------------------*/ 57 58 .globl c_runtime_cpu_setup 59c_runtime_cpu_setup: 60 61 mov pc, lr 62 63/* 64 ************************************************************************* 65 * 66 * CPU_init_critical registers 67 * 68 * setup important registers 69 * setup memory timing 70 * 71 ************************************************************************* 72 */ 73 74 75#ifndef CONFIG_SKIP_LOWLEVEL_INIT 76cpu_init_crit: 77 /* 78 * flush v4 I/D caches 79 */ 80 mov r0, #0 81 mcr p15, 0, r0, c7, c5, 0 /* flush v4 I-cache */ 82 mcr p15, 0, r0, c7, c6, 0 /* flush v4 D-cache */ 83 84 /* 85 * disable MMU stuff and caches 86 */ 87 mrc p15, 0, r0, c1, c0, 0 88 bic r0, r0, #0x00002300 /* clear bits 13, 9:8 (--V- --RS) */ 89 bic r0, r0, #0x00000087 /* clear bits 7, 2:0 (B--- -CAM) */ 90 orr r0, r0, #0x00000002 /* set bit 2 (A) Align */ 91 orr r0, r0, #0x00001000 /* set bit 12 (I) I-Cache */ 92 mcr p15, 0, r0, c1, c0, 0 93 94 /* 95 * Go setup Memory and board specific bits prior to relocation. 96 */ 97 mov ip, lr /* perserve link reg across call */ 98 bl lowlevel_init /* go setup memory */ 99 mov lr, ip /* restore link */ 100 mov pc, lr /* back to my caller */ 101#endif 102