1/* 2 * armboot - Startup Code for ARM926EJS CPU-core 3 * 4 * Copyright (c) 2003 Texas Instruments 5 * 6 * ----- Adapted for OMAP1610 OMAP730 from ARM925t code ------ 7 * 8 * Copyright (c) 2001 Marius Gröger <mag@sysgo.de> 9 * Copyright (c) 2002 Alex Züpke <azu@sysgo.de> 10 * Copyright (c) 2002 Gary Jennejohn <garyj@denx.de> 11 * Copyright (c) 2003 Richard Woodruff <r-woodruff2@ti.com> 12 * Copyright (c) 2003 Kshitij <kshitij@ti.com> 13 * Copyright (c) 2010 Albert Aribaud <albert.u.boot@aribaud.net> 14 * 15 * See file CREDITS for list of people who contributed to this 16 * project. 17 * 18 * This program is free software; you can redistribute it and/or 19 * modify it under the terms of the GNU General Public License as 20 * published by the Free Software Foundation; either version 2 of 21 * the License, or (at your option) any later version. 22 * 23 * This program is distributed in the hope that it will be useful, 24 * but WITHOUT ANY WARRANTY; without even the implied warranty of 25 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 26 * GNU General Public License for more details. 27 * 28 * You should have received a copy of the GNU General Public License 29 * along with this program; if not, write to the Free Software 30 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 31 * MA 02111-1307 USA 32 */ 33 34#include <asm-offsets.h> 35#include <config.h> 36#include <version.h> 37 38/* 39 ************************************************************************* 40 * 41 * Jump vector table as in table 3.1 in [1] 42 * 43 ************************************************************************* 44 */ 45 46 47.globl _start 48_start: 49 b reset 50 ldr pc, _undefined_instruction 51 ldr pc, _software_interrupt 52 ldr pc, _prefetch_abort 53 ldr pc, _data_abort 54 ldr pc, _not_used 55 ldr pc, _irq 56 ldr pc, _fiq 57 58_undefined_instruction: 59 .word undefined_instruction 60_software_interrupt: 61 .word software_interrupt 62_prefetch_abort: 63 .word prefetch_abort 64_data_abort: 65 .word data_abort 66_not_used: 67 .word not_used 68_irq: 69 .word irq 70_fiq: 71 .word fiq 72 73 .balignl 16,0xdeadbeef 74 75_vectors_end: 76 77/* 78 ************************************************************************* 79 * 80 * Startup Code (reset vector) 81 * 82 * do important init only if we don't start from memory! 83 * setup Memory and board specific bits prior to relocation. 84 * relocate armboot to ram 85 * setup stack 86 * 87 ************************************************************************* 88 */ 89 90.globl _TEXT_BASE 91_TEXT_BASE: 92 .word CONFIG_SYS_TEXT_BASE 93 94/* 95 * These are defined in the board-specific linker script. 96 * Subtracting _start from them lets the linker put their 97 * relative position in the executable instead of leaving 98 * them null. 99 */ 100.globl _bss_start_ofs 101_bss_start_ofs: 102 .word __bss_start - _start 103 104.globl _bss_end_ofs 105_bss_end_ofs: 106 .word __bss_end__ - _start 107 108.globl _end_ofs 109_end_ofs: 110 .word _end - _start 111 112#ifdef CONFIG_USE_IRQ 113/* IRQ stack memory (calculated at run-time) */ 114.globl IRQ_STACK_START 115IRQ_STACK_START: 116 .word 0x0badc0de 117 118/* IRQ stack memory (calculated at run-time) */ 119.globl FIQ_STACK_START 120FIQ_STACK_START: 121 .word 0x0badc0de 122#endif 123 124/* IRQ stack memory (calculated at run-time) + 8 bytes */ 125.globl IRQ_STACK_START_IN 126IRQ_STACK_START_IN: 127 .word 0x0badc0de 128 129/* 130 * the actual reset code 131 */ 132 133reset: 134 /* 135 * set the cpu to SVC32 mode 136 */ 137 mrs r0,cpsr 138 bic r0,r0,#0x1f 139 orr r0,r0,#0xd3 140 msr cpsr,r0 141 142 /* 143 * we do sys-critical inits only at reboot, 144 * not when booting from ram! 145 */ 146#ifndef CONFIG_SKIP_LOWLEVEL_INIT 147 bl cpu_init_crit 148#endif 149 150 bl _main 151 152/*------------------------------------------------------------------------------*/ 153 154/* 155 * void relocate_code (addr_sp, gd, addr_moni) 156 * 157 * This "function" does not return, instead it continues in RAM 158 * after relocating the monitor code. 159 * 160 */ 161 .globl relocate_code 162relocate_code: 163 mov r4, r0 /* save addr_sp */ 164 mov r5, r1 /* save addr of gd */ 165 mov r6, r2 /* save addr of destination */ 166 167 adr r0, _start 168 cmp r0, r6 169 moveq r9, #0 /* no relocation. relocation offset(r9) = 0 */ 170 beq relocate_done /* skip relocation */ 171 mov r1, r6 /* r1 <- scratch for copy_loop */ 172 ldr r3, _bss_start_ofs 173 add r2, r0, r3 /* r2 <- source end address */ 174 175copy_loop: 176 ldmia r0!, {r9-r10} /* copy from source address [r0] */ 177 stmia r1!, {r9-r10} /* copy to target address [r1] */ 178 cmp r0, r2 /* until source end address [r2] */ 179 blo copy_loop 180 181#ifndef CONFIG_SPL_BUILD 182 /* 183 * fix .rel.dyn relocations 184 */ 185 ldr r0, _TEXT_BASE /* r0 <- Text base */ 186 sub r9, r6, r0 /* r9 <- relocation offset */ 187 ldr r10, _dynsym_start_ofs /* r10 <- sym table ofs */ 188 add r10, r10, r0 /* r10 <- sym table in FLASH */ 189 ldr r2, _rel_dyn_start_ofs /* r2 <- rel dyn start ofs */ 190 add r2, r2, r0 /* r2 <- rel dyn start in FLASH */ 191 ldr r3, _rel_dyn_end_ofs /* r3 <- rel dyn end ofs */ 192 add r3, r3, r0 /* r3 <- rel dyn end in FLASH */ 193fixloop: 194 ldr r0, [r2] /* r0 <- location to fix up, IN FLASH! */ 195 add r0, r0, r9 /* r0 <- location to fix up in RAM */ 196 ldr r1, [r2, #4] 197 and r7, r1, #0xff 198 cmp r7, #23 /* relative fixup? */ 199 beq fixrel 200 cmp r7, #2 /* absolute fixup? */ 201 beq fixabs 202 /* ignore unknown type of fixup */ 203 b fixnext 204fixabs: 205 /* absolute fix: set location to (offset) symbol value */ 206 mov r1, r1, LSR #4 /* r1 <- symbol index in .dynsym */ 207 add r1, r10, r1 /* r1 <- address of symbol in table */ 208 ldr r1, [r1, #4] /* r1 <- symbol value */ 209 add r1, r1, r9 /* r1 <- relocated sym addr */ 210 b fixnext 211fixrel: 212 /* relative fix: increase location by offset */ 213 ldr r1, [r0] 214 add r1, r1, r9 215fixnext: 216 str r1, [r0] 217 add r2, r2, #8 /* each rel.dyn entry is 8 bytes */ 218 cmp r2, r3 219 blo fixloop 220#endif 221 222relocate_done: 223 224 mov pc, lr 225 226_rel_dyn_start_ofs: 227 .word __rel_dyn_start - _start 228_rel_dyn_end_ofs: 229 .word __rel_dyn_end - _start 230_dynsym_start_ofs: 231 .word __dynsym_start - _start 232 233 .globl c_runtime_cpu_setup 234c_runtime_cpu_setup: 235 236 mov pc, lr 237 238/* 239 ************************************************************************* 240 * 241 * CPU_init_critical registers 242 * 243 * setup important registers 244 * setup memory timing 245 * 246 ************************************************************************* 247 */ 248 249 250#ifndef CONFIG_SKIP_LOWLEVEL_INIT 251cpu_init_crit: 252 /* 253 * flush v4 I/D caches 254 */ 255 mov r0, #0 256 mcr p15, 0, r0, c7, c5, 0 /* flush v4 I-cache */ 257 mcr p15, 0, r0, c7, c6, 0 /* flush v4 D-cache */ 258 259 /* 260 * disable MMU stuff and caches 261 */ 262 mrc p15, 0, r0, c1, c0, 0 263 bic r0, r0, #0x00002300 /* clear bits 13, 9:8 (--V- --RS) */ 264 bic r0, r0, #0x00000087 /* clear bits 7, 2:0 (B--- -CAM) */ 265 orr r0, r0, #0x00000002 /* set bit 2 (A) Align */ 266 orr r0, r0, #0x00001000 /* set bit 12 (I) I-Cache */ 267 mcr p15, 0, r0, c1, c0, 0 268 269 /* 270 * Go setup Memory and board specific bits prior to relocation. 271 */ 272 mov ip, lr /* perserve link reg across call */ 273 bl lowlevel_init /* go setup memory */ 274 mov lr, ip /* restore link */ 275 mov pc, lr /* back to my caller */ 276#endif 277/* 278 ************************************************************************* 279 * 280 * Interrupt handling 281 * 282 ************************************************************************* 283 */ 284 285@ 286@ IRQ stack frame. 287@ 288#define S_FRAME_SIZE 72 289 290#define S_OLD_R0 68 291#define S_PSR 64 292#define S_PC 60 293#define S_LR 56 294#define S_SP 52 295 296#define S_IP 48 297#define S_FP 44 298#define S_R10 40 299#define S_R9 36 300#define S_R8 32 301#define S_R7 28 302#define S_R6 24 303#define S_R5 20 304#define S_R4 16 305#define S_R3 12 306#define S_R2 8 307#define S_R1 4 308#define S_R0 0 309 310#define MODE_SVC 0x13 311#define I_BIT 0x80 312 313/* 314 * use bad_save_user_regs for abort/prefetch/undef/swi ... 315 * use irq_save_user_regs / irq_restore_user_regs for IRQ/FIQ handling 316 */ 317 318 .macro bad_save_user_regs 319 @ carve out a frame on current user stack 320 sub sp, sp, #S_FRAME_SIZE 321 stmia sp, {r0 - r12} @ Save user registers (now in svc mode) r0-r12 322 323 ldr r2, IRQ_STACK_START_IN 324 @ get values for "aborted" pc and cpsr (into parm regs) 325 ldmia r2, {r2 - r3} 326 add r0, sp, #S_FRAME_SIZE @ grab pointer to old stack 327 add r5, sp, #S_SP 328 mov r1, lr 329 stmia r5, {r0 - r3} @ save sp_SVC, lr_SVC, pc, cpsr 330 mov r0, sp @ save current stack into r0 (param register) 331 .endm 332 333 .macro irq_save_user_regs 334 sub sp, sp, #S_FRAME_SIZE 335 stmia sp, {r0 - r12} @ Calling r0-r12 336 @ !!!! R8 NEEDS to be saved !!!! a reserved stack spot would be good. 337 add r8, sp, #S_PC 338 stmdb r8, {sp, lr}^ @ Calling SP, LR 339 str lr, [r8, #0] @ Save calling PC 340 mrs r6, spsr 341 str r6, [r8, #4] @ Save CPSR 342 str r0, [r8, #8] @ Save OLD_R0 343 mov r0, sp 344 .endm 345 346 .macro irq_restore_user_regs 347 ldmia sp, {r0 - lr}^ @ Calling r0 - lr 348 mov r0, r0 349 ldr lr, [sp, #S_PC] @ Get PC 350 add sp, sp, #S_FRAME_SIZE 351 subs pc, lr, #4 @ return & move spsr_svc into cpsr 352 .endm 353 354 .macro get_bad_stack 355 ldr r13, IRQ_STACK_START_IN @ setup our mode stack 356 357 str lr, [r13] @ save caller lr in position 0 of saved stack 358 mrs lr, spsr @ get the spsr 359 str lr, [r13, #4] @ save spsr in position 1 of saved stack 360 mov r13, #MODE_SVC @ prepare SVC-Mode 361 @ msr spsr_c, r13 362 msr spsr, r13 @ switch modes, make sure moves will execute 363 mov lr, pc @ capture return pc 364 movs pc, lr @ jump to next instruction & switch modes. 365 .endm 366 367 .macro get_irq_stack @ setup IRQ stack 368 ldr sp, IRQ_STACK_START 369 .endm 370 371 .macro get_fiq_stack @ setup FIQ stack 372 ldr sp, FIQ_STACK_START 373 .endm 374 375/* 376 * exception handlers 377 */ 378 .align 5 379undefined_instruction: 380 get_bad_stack 381 bad_save_user_regs 382 bl do_undefined_instruction 383 384 .align 5 385software_interrupt: 386 get_bad_stack 387 bad_save_user_regs 388 bl do_software_interrupt 389 390 .align 5 391prefetch_abort: 392 get_bad_stack 393 bad_save_user_regs 394 bl do_prefetch_abort 395 396 .align 5 397data_abort: 398 get_bad_stack 399 bad_save_user_regs 400 bl do_data_abort 401 402 .align 5 403not_used: 404 get_bad_stack 405 bad_save_user_regs 406 bl do_not_used 407 408#ifdef CONFIG_USE_IRQ 409 410 .align 5 411irq: 412 get_irq_stack 413 irq_save_user_regs 414 bl do_irq 415 irq_restore_user_regs 416 417 .align 5 418fiq: 419 get_fiq_stack 420 /* someone ought to write a more effiction fiq_save_user_regs */ 421 irq_save_user_regs 422 bl do_fiq 423 irq_restore_user_regs 424 425#else 426 427 .align 5 428irq: 429 get_bad_stack 430 bad_save_user_regs 431 bl do_irq 432 433 .align 5 434fiq: 435 get_bad_stack 436 bad_save_user_regs 437 bl do_fiq 438 439#endif 440 441# ifdef CONFIG_INTEGRATOR 442 443 /* Satisfied by general board level routine */ 444 445#else 446 447 .align 5 448.globl reset_cpu 449reset_cpu: 450 451 ldr r1, rstctl1 /* get clkm1 reset ctl */ 452 mov r3, #0x0 453 strh r3, [r1] /* clear it */ 454 mov r3, #0x8 455 strh r3, [r1] /* force dsp+arm reset */ 456_loop_forever: 457 b _loop_forever 458 459rstctl1: 460 .word 0xfffece10 461 462#endif /* #ifdef CONFIG_INTEGRATOR */ 463