xref: /openbmc/u-boot/arch/arm/cpu/arm946es/start.S (revision 872cfa20)
1/* SPDX-License-Identifier: GPL-2.0+ */
2/*
3 *  armboot - Startup Code for ARM926EJS CPU-core
4 *
5 *  Copyright (c) 2003  Texas Instruments
6 *
7 *  ----- Adapted for OMAP1610 OMAP730 from ARM925t code ------
8 *
9 *  Copyright (c) 2001	Marius Gröger <mag@sysgo.de>
10 *  Copyright (c) 2002	Alex Züpke <azu@sysgo.de>
11 *  Copyright (c) 2002	Gary Jennejohn <garyj@denx.de>
12 *  Copyright (c) 2003	Richard Woodruff <r-woodruff2@ti.com>
13 *  Copyright (c) 2003	Kshitij <kshitij@ti.com>
14 *  Copyright (c) 2010	Albert Aribaud <albert.u.boot@aribaud.net>
15 */
16
17#include <asm-offsets.h>
18#include <config.h>
19
20/*
21 *************************************************************************
22 *
23 * Startup Code (reset vector)
24 *
25 * do important init only if we don't start from memory!
26 * setup Memory and board specific bits prior to relocation.
27 * relocate armboot to ram
28 * setup stack
29 *
30 *************************************************************************
31 */
32
33	.globl	reset
34
35reset:
36	/*
37	 * set the cpu to SVC32 mode
38	 */
39	mrs	r0,cpsr
40	bic	r0,r0,#0x1f
41	orr	r0,r0,#0xd3
42	msr	cpsr,r0
43
44	/*
45	 * we do sys-critical inits only at reboot,
46	 * not when booting from ram!
47	 */
48#ifndef CONFIG_SKIP_LOWLEVEL_INIT
49	bl	cpu_init_crit
50#endif
51
52	bl	_main
53
54/*------------------------------------------------------------------------------*/
55
56	.globl	c_runtime_cpu_setup
57c_runtime_cpu_setup:
58
59	mov	pc, lr
60
61/*
62 *************************************************************************
63 *
64 * CPU_init_critical registers
65 *
66 * setup important registers
67 * setup memory timing
68 *
69 *************************************************************************
70 */
71
72
73#ifndef CONFIG_SKIP_LOWLEVEL_INIT
74cpu_init_crit:
75	/*
76	 * flush v4 I/D caches
77	 */
78	mov	r0, #0
79	mcr	p15, 0, r0, c7, c5, 0	/* flush v4 I-cache */
80	mcr	p15, 0, r0, c7, c6, 0	/* flush v4 D-cache */
81
82	/*
83	 * disable MMU stuff and caches
84	 */
85	mrc	p15, 0, r0, c1, c0, 0
86	bic	r0, r0, #0x00002300	/* clear bits 13, 9:8 (--V- --RS) */
87	bic	r0, r0, #0x00000087	/* clear bits 7, 2:0 (B--- -CAM) */
88	orr	r0, r0, #0x00000002	/* set bit 1 (A) Align */
89	orr	r0, r0, #0x00001000	/* set bit 12 (I) I-Cache */
90	mcr	p15, 0, r0, c1, c0, 0
91
92#ifndef CONFIG_SKIP_LOWLEVEL_INIT_ONLY
93	/*
94	 * Go setup Memory and board specific bits prior to relocation.
95	 */
96	mov	ip, lr		/* perserve link reg across call */
97	bl	lowlevel_init	/* go setup memory */
98	mov	lr, ip		/* restore link */
99#endif
100	mov	pc, lr		/* back to my caller */
101#endif
102