xref: /openbmc/u-boot/arch/arm/cpu/arm946es/start.S (revision 29b103c7)
1/*
2 *  armboot - Startup Code for ARM926EJS CPU-core
3 *
4 *  Copyright (c) 2003  Texas Instruments
5 *
6 *  ----- Adapted for OMAP1610 OMAP730 from ARM925t code ------
7 *
8 *  Copyright (c) 2001	Marius Gröger <mag@sysgo.de>
9 *  Copyright (c) 2002	Alex Züpke <azu@sysgo.de>
10 *  Copyright (c) 2002	Gary Jennejohn <garyj@denx.de>
11 *  Copyright (c) 2003	Richard Woodruff <r-woodruff2@ti.com>
12 *  Copyright (c) 2003	Kshitij <kshitij@ti.com>
13 *  Copyright (c) 2010	Albert Aribaud <albert.u.boot@aribaud.net>
14 *
15 * SPDX-License-Identifier:	GPL-2.0+
16 */
17
18#include <asm-offsets.h>
19#include <config.h>
20
21/*
22 *************************************************************************
23 *
24 * Startup Code (reset vector)
25 *
26 * do important init only if we don't start from memory!
27 * setup Memory and board specific bits prior to relocation.
28 * relocate armboot to ram
29 * setup stack
30 *
31 *************************************************************************
32 */
33
34	.globl	reset
35
36reset:
37	/*
38	 * set the cpu to SVC32 mode
39	 */
40	mrs	r0,cpsr
41	bic	r0,r0,#0x1f
42	orr	r0,r0,#0xd3
43	msr	cpsr,r0
44
45	/*
46	 * we do sys-critical inits only at reboot,
47	 * not when booting from ram!
48	 */
49#ifndef CONFIG_SKIP_LOWLEVEL_INIT
50	bl	cpu_init_crit
51#endif
52
53	bl	_main
54
55/*------------------------------------------------------------------------------*/
56
57	.globl	c_runtime_cpu_setup
58c_runtime_cpu_setup:
59
60	mov	pc, lr
61
62/*
63 *************************************************************************
64 *
65 * CPU_init_critical registers
66 *
67 * setup important registers
68 * setup memory timing
69 *
70 *************************************************************************
71 */
72
73
74#ifndef CONFIG_SKIP_LOWLEVEL_INIT
75cpu_init_crit:
76	/*
77	 * flush v4 I/D caches
78	 */
79	mov	r0, #0
80	mcr	p15, 0, r0, c7, c5, 0	/* flush v4 I-cache */
81	mcr	p15, 0, r0, c7, c6, 0	/* flush v4 D-cache */
82
83	/*
84	 * disable MMU stuff and caches
85	 */
86	mrc	p15, 0, r0, c1, c0, 0
87	bic	r0, r0, #0x00002300	/* clear bits 13, 9:8 (--V- --RS) */
88	bic	r0, r0, #0x00000087	/* clear bits 7, 2:0 (B--- -CAM) */
89	orr	r0, r0, #0x00000002	/* set bit 2 (A) Align */
90	orr	r0, r0, #0x00001000	/* set bit 12 (I) I-Cache */
91	mcr	p15, 0, r0, c1, c0, 0
92
93	/*
94	 * Go setup Memory and board specific bits prior to relocation.
95	 */
96	mov	ip, lr		/* perserve link reg across call */
97	bl	lowlevel_init	/* go setup memory */
98	mov	lr, ip		/* restore link */
99	mov	pc, lr		/* back to my caller */
100#endif
101