xref: /openbmc/u-boot/arch/arm/cpu/arm946es/start.S (revision 1e52fea3) 
1/*
2 *  armboot - Startup Code for ARM926EJS CPU-core
3 *
4 *  Copyright (c) 2003  Texas Instruments
5 *
6 *  ----- Adapted for OMAP1610 OMAP730 from ARM925t code ------
7 *
8 *  Copyright (c) 2001	Marius Gröger <mag@sysgo.de>
9 *  Copyright (c) 2002	Alex Züpke <azu@sysgo.de>
10 *  Copyright (c) 2002	Gary Jennejohn <garyj@denx.de>
11 *  Copyright (c) 2003	Richard Woodruff <r-woodruff2@ti.com>
12 *  Copyright (c) 2003	Kshitij <kshitij@ti.com>
13 *  Copyright (c) 2010	Albert Aribaud <albert.u.boot@aribaud.net>
14 *
15 * See file CREDITS for list of people who contributed to this
16 * project.
17 *
18 * This program is free software; you can redistribute it and/or
19 * modify it under the terms of the GNU General Public License as
20 * published by the Free Software Foundation; either version 2 of
21 * the License, or (at your option) any later version.
22 *
23 * This program is distributed in the hope that it will be useful,
24 * but WITHOUT ANY WARRANTY; without even the implied warranty of
25 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
26 * GNU General Public License for more details.
27 *
28 * You should have received a copy of the GNU General Public License
29 * along with this program; if not, write to the Free Software
30 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
31 * MA 02111-1307 USA
32 */
33
34#include <asm-offsets.h>
35#include <config.h>
36#include <version.h>
37
38/*
39 *************************************************************************
40 *
41 * Jump vector table as in table 3.1 in [1]
42 *
43 *************************************************************************
44 */
45
46
47.globl _start
48_start:
49	b	reset
50	ldr	pc, _undefined_instruction
51	ldr	pc, _software_interrupt
52	ldr	pc, _prefetch_abort
53	ldr	pc, _data_abort
54	ldr	pc, _not_used
55	ldr	pc, _irq
56	ldr	pc, _fiq
57
58_undefined_instruction:
59	.word undefined_instruction
60_software_interrupt:
61	.word software_interrupt
62_prefetch_abort:
63	.word prefetch_abort
64_data_abort:
65	.word data_abort
66_not_used:
67	.word not_used
68_irq:
69	.word irq
70_fiq:
71	.word fiq
72
73	.balignl 16,0xdeadbeef
74
75_vectors_end:
76
77/*
78 *************************************************************************
79 *
80 * Startup Code (reset vector)
81 *
82 * do important init only if we don't start from memory!
83 * setup Memory and board specific bits prior to relocation.
84 * relocate armboot to ram
85 * setup stack
86 *
87 *************************************************************************
88 */
89
90.globl _TEXT_BASE
91_TEXT_BASE:
92	.word	CONFIG_SYS_TEXT_BASE
93
94/*
95 * These are defined in the board-specific linker script.
96 * Subtracting _start from them lets the linker put their
97 * relative position in the executable instead of leaving
98 * them null.
99 */
100.globl _bss_start_ofs
101_bss_start_ofs:
102	.word __bss_start - _start
103
104.globl _bss_end_ofs
105_bss_end_ofs:
106	.word __bss_end__ - _start
107
108.globl _end_ofs
109_end_ofs:
110	.word _end - _start
111
112#ifdef CONFIG_USE_IRQ
113/* IRQ stack memory (calculated at run-time) */
114.globl IRQ_STACK_START
115IRQ_STACK_START:
116	.word	0x0badc0de
117
118/* IRQ stack memory (calculated at run-time) */
119.globl FIQ_STACK_START
120FIQ_STACK_START:
121	.word 0x0badc0de
122#endif
123
124/* IRQ stack memory (calculated at run-time) + 8 bytes */
125.globl IRQ_STACK_START_IN
126IRQ_STACK_START_IN:
127	.word	0x0badc0de
128
129/*
130 * the actual reset code
131 */
132
133reset:
134	/*
135	 * set the cpu to SVC32 mode
136	 */
137	mrs	r0,cpsr
138	bic	r0,r0,#0x1f
139	orr	r0,r0,#0xd3
140	msr	cpsr,r0
141
142	/*
143	 * we do sys-critical inits only at reboot,
144	 * not when booting from ram!
145	 */
146#ifndef CONFIG_SKIP_LOWLEVEL_INIT
147	bl	cpu_init_crit
148#endif
149
150/* Set stackpointer in internal RAM to call board_init_f */
151call_board_init_f:
152	ldr	sp, =(CONFIG_SYS_INIT_SP_ADDR)
153	bic	sp, sp, #7 /* 8-byte alignment for ABI compliance */
154	ldr	r0,=0x00000000
155	bl	board_init_f
156
157/*------------------------------------------------------------------------------*/
158
159/*
160 * void relocate_code (addr_sp, gd, addr_moni)
161 *
162 * This "function" does not return, instead it continues in RAM
163 * after relocating the monitor code.
164 *
165 */
166	.globl	relocate_code
167relocate_code:
168	mov	r4, r0	/* save addr_sp */
169	mov	r5, r1	/* save addr of gd */
170	mov	r6, r2	/* save addr of destination */
171
172	/* Set up the stack						    */
173stack_setup:
174	mov	sp, r4
175
176	adr	r0, _start
177	cmp	r0, r6
178	beq	clear_bss		/* skip relocation */
179	mov	r1, r6			/* r1 <- scratch for copy_loop */
180	ldr	r3, _bss_start_ofs
181	add	r2, r0, r3		/* r2 <- source end address	    */
182
183copy_loop:
184	ldmia	r0!, {r9-r10}		/* copy from source address [r0]    */
185	stmia	r1!, {r9-r10}		/* copy to   target address [r1]    */
186	cmp	r0, r2			/* until source end address [r2]    */
187	blo	copy_loop
188
189#ifndef CONFIG_SPL_BUILD
190	/*
191	 * fix .rel.dyn relocations
192	 */
193	ldr	r0, _TEXT_BASE		/* r0 <- Text base */
194	sub	r9, r6, r0		/* r9 <- relocation offset */
195	ldr	r10, _dynsym_start_ofs	/* r10 <- sym table ofs */
196	add	r10, r10, r0		/* r10 <- sym table in FLASH */
197	ldr	r2, _rel_dyn_start_ofs	/* r2 <- rel dyn start ofs */
198	add	r2, r2, r0		/* r2 <- rel dyn start in FLASH */
199	ldr	r3, _rel_dyn_end_ofs	/* r3 <- rel dyn end ofs */
200	add	r3, r3, r0		/* r3 <- rel dyn end in FLASH */
201fixloop:
202	ldr	r0, [r2]		/* r0 <- location to fix up, IN FLASH! */
203	add	r0, r0, r9		/* r0 <- location to fix up in RAM */
204	ldr	r1, [r2, #4]
205	and	r7, r1, #0xff
206	cmp	r7, #23			/* relative fixup? */
207	beq	fixrel
208	cmp	r7, #2			/* absolute fixup? */
209	beq	fixabs
210	/* ignore unknown type of fixup */
211	b	fixnext
212fixabs:
213	/* absolute fix: set location to (offset) symbol value */
214	mov	r1, r1, LSR #4		/* r1 <- symbol index in .dynsym */
215	add	r1, r10, r1		/* r1 <- address of symbol in table */
216	ldr	r1, [r1, #4]		/* r1 <- symbol value */
217	add	r1, r1, r9		/* r1 <- relocated sym addr */
218	b	fixnext
219fixrel:
220	/* relative fix: increase location by offset */
221	ldr	r1, [r0]
222	add	r1, r1, r9
223fixnext:
224	str	r1, [r0]
225	add	r2, r2, #8		/* each rel.dyn entry is 8 bytes */
226	cmp	r2, r3
227	blo	fixloop
228#endif
229
230clear_bss:
231#ifndef CONFIG_SPL_BUILD
232	ldr	r0, _bss_start_ofs
233	ldr	r1, _bss_end_ofs
234	mov	r4, r6			/* reloc addr */
235	add	r0, r0, r4
236	add	r1, r1, r4
237	mov	r2, #0x00000000		/* clear			    */
238
239clbss_l:str	r2, [r0]		/* clear loop...		    */
240	add	r0, r0, #4
241	cmp	r0, r1
242	blo	clbss_l
243#endif
244
245/*
246 * We are done. Do not return, instead branch to second part of board
247 * initialization, now running from RAM.
248 */
249#ifdef CONFIG_NAND_SPL
250	ldr     pc, _nand_boot
251
252_nand_boot: .word nand_boot
253#else
254	ldr	r0, _board_init_r_ofs
255	adr	r1, _start
256	add	lr, r0, r1
257	add	lr, lr, r9
258	/* setup parameters for board_init_r */
259	mov	r0, r5		/* gd_t */
260	mov	r1, r6		/* dest_addr */
261	/* jump to it ... */
262	mov	pc, lr
263
264_board_init_r_ofs:
265	.word board_init_r - _start
266#endif
267
268_rel_dyn_start_ofs:
269	.word __rel_dyn_start - _start
270_rel_dyn_end_ofs:
271	.word __rel_dyn_end - _start
272_dynsym_start_ofs:
273	.word __dynsym_start - _start
274
275/*
276 *************************************************************************
277 *
278 * CPU_init_critical registers
279 *
280 * setup important registers
281 * setup memory timing
282 *
283 *************************************************************************
284 */
285
286
287#ifndef CONFIG_SKIP_LOWLEVEL_INIT
288cpu_init_crit:
289	/*
290	 * flush v4 I/D caches
291	 */
292	mov	r0, #0
293	mcr	p15, 0, r0, c7, c5, 0	/* flush v4 I-cache */
294	mcr	p15, 0, r0, c7, c6, 0	/* flush v4 D-cache */
295
296	/*
297	 * disable MMU stuff and caches
298	 */
299	mrc	p15, 0, r0, c1, c0, 0
300	bic	r0, r0, #0x00002300	/* clear bits 13, 9:8 (--V- --RS) */
301	bic	r0, r0, #0x00000087	/* clear bits 7, 2:0 (B--- -CAM) */
302	orr	r0, r0, #0x00000002	/* set bit 2 (A) Align */
303	orr	r0, r0, #0x00001000	/* set bit 12 (I) I-Cache */
304	mcr	p15, 0, r0, c1, c0, 0
305
306	/*
307	 * Go setup Memory and board specific bits prior to relocation.
308	 */
309	mov	ip, lr		/* perserve link reg across call */
310	bl	lowlevel_init	/* go setup memory */
311	mov	lr, ip		/* restore link */
312	mov	pc, lr		/* back to my caller */
313#endif
314/*
315 *************************************************************************
316 *
317 * Interrupt handling
318 *
319 *************************************************************************
320 */
321
322@
323@ IRQ stack frame.
324@
325#define S_FRAME_SIZE	72
326
327#define S_OLD_R0	68
328#define S_PSR		64
329#define S_PC		60
330#define S_LR		56
331#define S_SP		52
332
333#define S_IP		48
334#define S_FP		44
335#define S_R10		40
336#define S_R9		36
337#define S_R8		32
338#define S_R7		28
339#define S_R6		24
340#define S_R5		20
341#define S_R4		16
342#define S_R3		12
343#define S_R2		8
344#define S_R1		4
345#define S_R0		0
346
347#define MODE_SVC 0x13
348#define I_BIT	 0x80
349
350/*
351 * use bad_save_user_regs for abort/prefetch/undef/swi ...
352 * use irq_save_user_regs / irq_restore_user_regs for IRQ/FIQ handling
353 */
354
355	.macro	bad_save_user_regs
356	@ carve out a frame on current user stack
357	sub	sp, sp, #S_FRAME_SIZE
358	stmia	sp, {r0 - r12}	@ Save user registers (now in svc mode) r0-r12
359
360	ldr	r2, IRQ_STACK_START_IN
361	@ get values for "aborted" pc and cpsr (into parm regs)
362	ldmia	r2, {r2 - r3}
363	add	r0, sp, #S_FRAME_SIZE		@ grab pointer to old stack
364	add	r5, sp, #S_SP
365	mov	r1, lr
366	stmia	r5, {r0 - r3}	@ save sp_SVC, lr_SVC, pc, cpsr
367	mov	r0, sp		@ save current stack into r0 (param register)
368	.endm
369
370	.macro	irq_save_user_regs
371	sub	sp, sp, #S_FRAME_SIZE
372	stmia	sp, {r0 - r12}			@ Calling r0-r12
373	@ !!!! R8 NEEDS to be saved !!!! a reserved stack spot would be good.
374	add	r8, sp, #S_PC
375	stmdb	r8, {sp, lr}^		@ Calling SP, LR
376	str	lr, [r8, #0]		@ Save calling PC
377	mrs	r6, spsr
378	str	r6, [r8, #4]		@ Save CPSR
379	str	r0, [r8, #8]		@ Save OLD_R0
380	mov	r0, sp
381	.endm
382
383	.macro	irq_restore_user_regs
384	ldmia	sp, {r0 - lr}^			@ Calling r0 - lr
385	mov	r0, r0
386	ldr	lr, [sp, #S_PC]			@ Get PC
387	add	sp, sp, #S_FRAME_SIZE
388	subs	pc, lr, #4		@ return & move spsr_svc into cpsr
389	.endm
390
391	.macro get_bad_stack
392	ldr	r13, IRQ_STACK_START_IN		@ setup our mode stack
393
394	str	lr, [r13]	@ save caller lr in position 0 of saved stack
395	mrs	lr, spsr	@ get the spsr
396	str	lr, [r13, #4]	@ save spsr in position 1 of saved stack
397	mov	r13, #MODE_SVC	@ prepare SVC-Mode
398	@ msr	spsr_c, r13
399	msr	spsr, r13	@ switch modes, make sure moves will execute
400	mov	lr, pc		@ capture return pc
401	movs	pc, lr		@ jump to next instruction & switch modes.
402	.endm
403
404	.macro get_irq_stack			@ setup IRQ stack
405	ldr	sp, IRQ_STACK_START
406	.endm
407
408	.macro get_fiq_stack			@ setup FIQ stack
409	ldr	sp, FIQ_STACK_START
410	.endm
411
412/*
413 * exception handlers
414 */
415	.align  5
416undefined_instruction:
417	get_bad_stack
418	bad_save_user_regs
419	bl	do_undefined_instruction
420
421	.align	5
422software_interrupt:
423	get_bad_stack
424	bad_save_user_regs
425	bl	do_software_interrupt
426
427	.align	5
428prefetch_abort:
429	get_bad_stack
430	bad_save_user_regs
431	bl	do_prefetch_abort
432
433	.align	5
434data_abort:
435	get_bad_stack
436	bad_save_user_regs
437	bl	do_data_abort
438
439	.align	5
440not_used:
441	get_bad_stack
442	bad_save_user_regs
443	bl	do_not_used
444
445#ifdef CONFIG_USE_IRQ
446
447	.align	5
448irq:
449	get_irq_stack
450	irq_save_user_regs
451	bl	do_irq
452	irq_restore_user_regs
453
454	.align	5
455fiq:
456	get_fiq_stack
457	/* someone ought to write a more effiction fiq_save_user_regs */
458	irq_save_user_regs
459	bl	do_fiq
460	irq_restore_user_regs
461
462#else
463
464	.align	5
465irq:
466	get_bad_stack
467	bad_save_user_regs
468	bl	do_irq
469
470	.align	5
471fiq:
472	get_bad_stack
473	bad_save_user_regs
474	bl	do_fiq
475
476#endif
477
478# ifdef CONFIG_INTEGRATOR
479
480	/* Satisfied by general board level routine */
481
482#else
483
484	.align	5
485.globl reset_cpu
486reset_cpu:
487
488	ldr	r1, rstctl1	/* get clkm1 reset ctl */
489	mov	r3, #0x0
490	strh	r3, [r1]	/* clear it */
491	mov	r3, #0x8
492	strh	r3, [r1]	/* force dsp+arm reset */
493_loop_forever:
494	b	_loop_forever
495
496rstctl1:
497	.word	0xfffece10
498
499#endif	/* #ifdef CONFIG_INTEGRATOR */
500