xref: /openbmc/u-boot/arch/arm/cpu/arm926ejs/start.S (revision dcac25a0) 
1/*
2 *  armboot - Startup Code for ARM926EJS CPU-core
3 *
4 *  Copyright (c) 2003  Texas Instruments
5 *
6 *  ----- Adapted for OMAP1610 OMAP730 from ARM925t code ------
7 *
8 *  Copyright (c) 2001	Marius Gr�ger <mag@sysgo.de>
9 *  Copyright (c) 2002	Alex Z�pke <azu@sysgo.de>
10 *  Copyright (c) 2002	Gary Jennejohn <garyj@denx.de>
11 *  Copyright (c) 2003	Richard Woodruff <r-woodruff2@ti.com>
12 *  Copyright (c) 2003	Kshitij <kshitij@ti.com>
13 *  Copyright (c) 2010	Albert Aribaud <albert.u.boot@aribaud.net>
14 *
15 * See file CREDITS for list of people who contributed to this
16 * project.
17 *
18 * This program is free software; you can redistribute it and/or
19 * modify it under the terms of the GNU General Public License as
20 * published by the Free Software Foundation; either version 2 of
21 * the License, or (at your option) any later version.
22 *
23 * This program is distributed in the hope that it will be useful,
24 * but WITHOUT ANY WARRANTY; without even the implied warranty of
25 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
26 * GNU General Public License for more details.
27 *
28 * You should have received a copy of the GNU General Public License
29 * along with this program; if not, write to the Free Software
30 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
31 * MA 02111-1307 USA
32 */
33
34#include <asm-offsets.h>
35#include <config.h>
36#include <common.h>
37#include <version.h>
38
39#if defined(CONFIG_OMAP1610)
40#include <./configs/omap1510.h>
41#elif defined(CONFIG_OMAP730)
42#include <./configs/omap730.h>
43#endif
44
45/*
46 *************************************************************************
47 *
48 * Jump vector table as in table 3.1 in [1]
49 *
50 *************************************************************************
51 */
52
53
54.globl _start
55_start:
56	b	reset
57#ifdef CONFIG_SPL_BUILD
58/* No exception handlers in preloader */
59	ldr	pc, _hang
60	ldr	pc, _hang
61	ldr	pc, _hang
62	ldr	pc, _hang
63	ldr	pc, _hang
64	ldr	pc, _hang
65	ldr	pc, _hang
66
67_hang:
68	.word	do_hang
69/* pad to 64 byte boundary */
70	.word	0x12345678
71	.word	0x12345678
72	.word	0x12345678
73	.word	0x12345678
74	.word	0x12345678
75	.word	0x12345678
76	.word	0x12345678
77#else
78	ldr	pc, _undefined_instruction
79	ldr	pc, _software_interrupt
80	ldr	pc, _prefetch_abort
81	ldr	pc, _data_abort
82	ldr	pc, _not_used
83	ldr	pc, _irq
84	ldr	pc, _fiq
85
86_undefined_instruction:
87	.word undefined_instruction
88_software_interrupt:
89	.word software_interrupt
90_prefetch_abort:
91	.word prefetch_abort
92_data_abort:
93	.word data_abort
94_not_used:
95	.word not_used
96_irq:
97	.word irq
98_fiq:
99	.word fiq
100
101#endif	/* CONFIG_SPL_BUILD */
102	.balignl 16,0xdeadbeef
103
104
105/*
106 *************************************************************************
107 *
108 * Startup Code (reset vector)
109 *
110 * do important init only if we don't start from memory!
111 * setup Memory and board specific bits prior to relocation.
112 * relocate armboot to ram
113 * setup stack
114 *
115 *************************************************************************
116 */
117
118.globl _TEXT_BASE
119_TEXT_BASE:
120	.word	CONFIG_SYS_TEXT_BASE
121
122/*
123 * These are defined in the board-specific linker script.
124 * Subtracting _start from them lets the linker put their
125 * relative position in the executable instead of leaving
126 * them null.
127 */
128.globl _bss_start_ofs
129_bss_start_ofs:
130	.word __bss_start - _start
131
132.globl _bss_end_ofs
133_bss_end_ofs:
134	.word __bss_end__ - _start
135
136.globl _end_ofs
137_end_ofs:
138	.word _end - _start
139
140#ifdef CONFIG_USE_IRQ
141/* IRQ stack memory (calculated at run-time) */
142.globl IRQ_STACK_START
143IRQ_STACK_START:
144	.word	0x0badc0de
145
146/* IRQ stack memory (calculated at run-time) */
147.globl FIQ_STACK_START
148FIQ_STACK_START:
149	.word 0x0badc0de
150#endif
151
152/* IRQ stack memory (calculated at run-time) + 8 bytes */
153.globl IRQ_STACK_START_IN
154IRQ_STACK_START_IN:
155	.word	0x0badc0de
156
157/*
158 * the actual reset code
159 */
160
161reset:
162	/*
163	 * set the cpu to SVC32 mode
164	 */
165	mrs	r0,cpsr
166	bic	r0,r0,#0x1f
167	orr	r0,r0,#0xd3
168	msr	cpsr,r0
169
170	/*
171	 * we do sys-critical inits only at reboot,
172	 * not when booting from ram!
173	 */
174#ifndef CONFIG_SKIP_LOWLEVEL_INIT
175	bl	cpu_init_crit
176#endif
177
178/* Set stackpointer in internal RAM to call board_init_f */
179call_board_init_f:
180	ldr	sp, =(CONFIG_SYS_INIT_SP_ADDR)
181	bic	sp, sp, #7 /* 8-byte alignment for ABI compliance */
182	ldr	r0,=0x00000000
183	bl	board_init_f
184
185/*------------------------------------------------------------------------------*/
186
187/*
188 * void relocate_code (addr_sp, gd, addr_moni)
189 *
190 * This "function" does not return, instead it continues in RAM
191 * after relocating the monitor code.
192 *
193 */
194	.globl	relocate_code
195relocate_code:
196	mov	r4, r0	/* save addr_sp */
197	mov	r5, r1	/* save addr of gd */
198	mov	r6, r2	/* save addr of destination */
199
200	/* Set up the stack						    */
201stack_setup:
202	mov	sp, r4
203
204	adr	r0, _start
205	cmp	r0, r6
206	beq	clear_bss		/* skip relocation */
207	mov	r1, r6			/* r1 <- scratch for copy loop */
208	ldr	r3, _bss_start_ofs
209	add	r2, r0, r3		/* r2 <- source end address	    */
210
211copy_loop:
212	ldmia	r0!, {r9-r10}		/* copy from source address [r0]    */
213	stmia	r1!, {r9-r10}		/* copy to   target address [r1]    */
214	cmp	r0, r2			/* until source end address [r2]    */
215	blo	copy_loop
216
217#ifndef CONFIG_SPL_BUILD
218	/*
219	 * fix .rel.dyn relocations
220	 */
221	ldr	r0, _TEXT_BASE		/* r0 <- Text base */
222	sub	r9, r6, r0		/* r9 <- relocation offset */
223	ldr	r10, _dynsym_start_ofs	/* r10 <- sym table ofs */
224	add	r10, r10, r0		/* r10 <- sym table in FLASH */
225	ldr	r2, _rel_dyn_start_ofs	/* r2 <- rel dyn start ofs */
226	add	r2, r2, r0		/* r2 <- rel dyn start in FLASH */
227	ldr	r3, _rel_dyn_end_ofs	/* r3 <- rel dyn end ofs */
228	add	r3, r3, r0		/* r3 <- rel dyn end in FLASH */
229fixloop:
230	ldr	r0, [r2]		/* r0 <- location to fix up, IN FLASH! */
231	add	r0, r0, r9		/* r0 <- location to fix up in RAM */
232	ldr	r1, [r2, #4]
233	and	r7, r1, #0xff
234	cmp	r7, #23			/* relative fixup? */
235	beq	fixrel
236	cmp	r7, #2			/* absolute fixup? */
237	beq	fixabs
238	/* ignore unknown type of fixup */
239	b	fixnext
240fixabs:
241	/* absolute fix: set location to (offset) symbol value */
242	mov	r1, r1, LSR #4		/* r1 <- symbol index in .dynsym */
243	add	r1, r10, r1		/* r1 <- address of symbol in table */
244	ldr	r1, [r1, #4]		/* r1 <- symbol value */
245	add	r1, r1, r9		/* r1 <- relocated sym addr */
246	b	fixnext
247fixrel:
248	/* relative fix: increase location by offset */
249	ldr	r1, [r0]
250	add	r1, r1, r9
251fixnext:
252	str	r1, [r0]
253	add	r2, r2, #8		/* each rel.dyn entry is 8 bytes */
254	cmp	r2, r3
255	blo	fixloop
256#endif
257
258clear_bss:
259#ifndef CONFIG_SPL_BUILD
260	ldr	r0, _bss_start_ofs
261	ldr	r1, _bss_end_ofs
262	mov	r4, r6			/* reloc addr */
263	add	r0, r0, r4
264	add	r1, r1, r4
265	mov	r2, #0x00000000		/* clear			    */
266
267clbss_l:str	r2, [r0]		/* clear loop...		    */
268	add	r0, r0, #4
269	cmp	r0, r1
270	bne	clbss_l
271
272	bl coloured_LED_init
273	bl red_LED_on
274#endif
275
276/*
277 * We are done. Do not return, instead branch to second part of board
278 * initialization, now running from RAM.
279 */
280#ifdef CONFIG_NAND_SPL
281	ldr     r0, _nand_boot_ofs
282	mov	pc, r0
283
284_nand_boot_ofs:
285	.word nand_boot
286#else
287	ldr	r0, _board_init_r_ofs
288	ldr	r1, _TEXT_BASE
289	add	lr, r0, r1
290	add	lr, lr, r9
291	/* setup parameters for board_init_r */
292	mov	r0, r5		/* gd_t */
293	mov	r1, r6		/* dest_addr */
294	/* jump to it ... */
295	mov	pc, lr
296
297_board_init_r_ofs:
298	.word board_init_r - _start
299#endif
300
301_rel_dyn_start_ofs:
302	.word __rel_dyn_start - _start
303_rel_dyn_end_ofs:
304	.word __rel_dyn_end - _start
305_dynsym_start_ofs:
306	.word __dynsym_start - _start
307
308/*
309 *************************************************************************
310 *
311 * CPU_init_critical registers
312 *
313 * setup important registers
314 * setup memory timing
315 *
316 *************************************************************************
317 */
318#ifndef CONFIG_SKIP_LOWLEVEL_INIT
319cpu_init_crit:
320	/*
321	 * flush v4 I/D caches
322	 */
323	mov	r0, #0
324	mcr	p15, 0, r0, c7, c7, 0	/* flush v3/v4 cache */
325	mcr	p15, 0, r0, c8, c7, 0	/* flush v4 TLB */
326
327	/*
328	 * disable MMU stuff and caches
329	 */
330	mrc	p15, 0, r0, c1, c0, 0
331	bic	r0, r0, #0x00002300	/* clear bits 13, 9:8 (--V- --RS) */
332	bic	r0, r0, #0x00000087	/* clear bits 7, 2:0 (B--- -CAM) */
333	orr	r0, r0, #0x00000002	/* set bit 2 (A) Align */
334	orr	r0, r0, #0x00001000	/* set bit 12 (I) I-Cache */
335	mcr	p15, 0, r0, c1, c0, 0
336
337	/*
338	 * Go setup Memory and board specific bits prior to relocation.
339	 */
340	mov	ip, lr		/* perserve link reg across call */
341	bl	lowlevel_init	/* go setup pll,mux,memory */
342	mov	lr, ip		/* restore link */
343	mov	pc, lr		/* back to my caller */
344#endif /* CONFIG_SKIP_LOWLEVEL_INIT */
345
346#ifndef CONFIG_SPL_BUILD
347/*
348 *************************************************************************
349 *
350 * Interrupt handling
351 *
352 *************************************************************************
353 */
354
355@
356@ IRQ stack frame.
357@
358#define S_FRAME_SIZE	72
359
360#define S_OLD_R0	68
361#define S_PSR		64
362#define S_PC		60
363#define S_LR		56
364#define S_SP		52
365
366#define S_IP		48
367#define S_FP		44
368#define S_R10		40
369#define S_R9		36
370#define S_R8		32
371#define S_R7		28
372#define S_R6		24
373#define S_R5		20
374#define S_R4		16
375#define S_R3		12
376#define S_R2		8
377#define S_R1		4
378#define S_R0		0
379
380#define MODE_SVC 0x13
381#define I_BIT	 0x80
382
383/*
384 * use bad_save_user_regs for abort/prefetch/undef/swi ...
385 * use irq_save_user_regs / irq_restore_user_regs for IRQ/FIQ handling
386 */
387
388	.macro	bad_save_user_regs
389	@ carve out a frame on current user stack
390	sub	sp, sp, #S_FRAME_SIZE
391	stmia	sp, {r0 - r12}	@ Save user registers (now in svc mode) r0-r12
392	ldr	r2, IRQ_STACK_START_IN
393	@ get values for "aborted" pc and cpsr (into parm regs)
394	ldmia	r2, {r2 - r3}
395	add	r0, sp, #S_FRAME_SIZE		@ grab pointer to old stack
396	add	r5, sp, #S_SP
397	mov	r1, lr
398	stmia	r5, {r0 - r3}	@ save sp_SVC, lr_SVC, pc, cpsr
399	mov	r0, sp		@ save current stack into r0 (param register)
400	.endm
401
402	.macro	irq_save_user_regs
403	sub	sp, sp, #S_FRAME_SIZE
404	stmia	sp, {r0 - r12}			@ Calling r0-r12
405	@ !!!! R8 NEEDS to be saved !!!! a reserved stack spot would be good.
406	add	r8, sp, #S_PC
407	stmdb	r8, {sp, lr}^		@ Calling SP, LR
408	str	lr, [r8, #0]		@ Save calling PC
409	mrs	r6, spsr
410	str	r6, [r8, #4]		@ Save CPSR
411	str	r0, [r8, #8]		@ Save OLD_R0
412	mov	r0, sp
413	.endm
414
415	.macro	irq_restore_user_regs
416	ldmia	sp, {r0 - lr}^			@ Calling r0 - lr
417	mov	r0, r0
418	ldr	lr, [sp, #S_PC]			@ Get PC
419	add	sp, sp, #S_FRAME_SIZE
420	subs	pc, lr, #4		@ return & move spsr_svc into cpsr
421	.endm
422
423	.macro get_bad_stack
424	ldr	r13, IRQ_STACK_START_IN		@ setup our mode stack
425
426	str	lr, [r13]	@ save caller lr in position 0 of saved stack
427	mrs	lr, spsr	@ get the spsr
428	str	lr, [r13, #4]	@ save spsr in position 1 of saved stack
429	mov	r13, #MODE_SVC	@ prepare SVC-Mode
430	@ msr	spsr_c, r13
431	msr	spsr, r13	@ switch modes, make sure moves will execute
432	mov	lr, pc		@ capture return pc
433	movs	pc, lr		@ jump to next instruction & switch modes.
434	.endm
435
436	.macro get_irq_stack			@ setup IRQ stack
437	ldr	sp, IRQ_STACK_START
438	.endm
439
440	.macro get_fiq_stack			@ setup FIQ stack
441	ldr	sp, FIQ_STACK_START
442	.endm
443#endif	/* CONFIG_SPL_BUILD */
444
445/*
446 * exception handlers
447 */
448#ifdef CONFIG_SPL_BUILD
449	.align	5
450do_hang:
451	ldr	sp, _TEXT_BASE			/* switch to abort stack */
4521:
453	bl	1b				/* hang and never return */
454#else	/* !CONFIG_SPL_BUILD */
455	.align  5
456undefined_instruction:
457	get_bad_stack
458	bad_save_user_regs
459	bl	do_undefined_instruction
460
461	.align	5
462software_interrupt:
463	get_bad_stack
464	bad_save_user_regs
465	bl	do_software_interrupt
466
467	.align	5
468prefetch_abort:
469	get_bad_stack
470	bad_save_user_regs
471	bl	do_prefetch_abort
472
473	.align	5
474data_abort:
475	get_bad_stack
476	bad_save_user_regs
477	bl	do_data_abort
478
479	.align	5
480not_used:
481	get_bad_stack
482	bad_save_user_regs
483	bl	do_not_used
484
485#ifdef CONFIG_USE_IRQ
486
487	.align	5
488irq:
489	get_irq_stack
490	irq_save_user_regs
491	bl	do_irq
492	irq_restore_user_regs
493
494	.align	5
495fiq:
496	get_fiq_stack
497	/* someone ought to write a more effiction fiq_save_user_regs */
498	irq_save_user_regs
499	bl	do_fiq
500	irq_restore_user_regs
501
502#else
503
504	.align	5
505irq:
506	get_bad_stack
507	bad_save_user_regs
508	bl	do_irq
509
510	.align	5
511fiq:
512	get_bad_stack
513	bad_save_user_regs
514	bl	do_fiq
515
516#endif
517#endif	/* CONFIG_SPL_BUILD */
518