xref: /openbmc/u-boot/arch/arm/cpu/arm926ejs/start.S (revision d7f71414) 
1/*
2 *  armboot - Startup Code for ARM926EJS CPU-core
3 *
4 *  Copyright (c) 2003  Texas Instruments
5 *
6 *  ----- Adapted for OMAP1610 OMAP730 from ARM925t code ------
7 *
8 *  Copyright (c) 2001	Marius Gröger <mag@sysgo.de>
9 *  Copyright (c) 2002	Alex Züpke <azu@sysgo.de>
10 *  Copyright (c) 2002	Gary Jennejohn <garyj@denx.de>
11 *  Copyright (c) 2003	Richard Woodruff <r-woodruff2@ti.com>
12 *  Copyright (c) 2003	Kshitij <kshitij@ti.com>
13 *  Copyright (c) 2010	Albert Aribaud <albert.u.boot@aribaud.net>
14 *
15 * See file CREDITS for list of people who contributed to this
16 * project.
17 *
18 * This program is free software; you can redistribute it and/or
19 * modify it under the terms of the GNU General Public License as
20 * published by the Free Software Foundation; either version 2 of
21 * the License, or (at your option) any later version.
22 *
23 * This program is distributed in the hope that it will be useful,
24 * but WITHOUT ANY WARRANTY; without even the implied warranty of
25 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
26 * GNU General Public License for more details.
27 *
28 * You should have received a copy of the GNU General Public License
29 * along with this program; if not, write to the Free Software
30 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
31 * MA 02111-1307 USA
32 */
33
34#include <asm-offsets.h>
35#include <config.h>
36#include <common.h>
37#include <version.h>
38
39#if defined(CONFIG_OMAP1610)
40#include <./configs/omap1510.h>
41#elif defined(CONFIG_OMAP730)
42#include <./configs/omap730.h>
43#endif
44
45/*
46 *************************************************************************
47 *
48 * Jump vector table as in table 3.1 in [1]
49 *
50 *************************************************************************
51 */
52
53
54#ifdef CONFIG_SYS_DV_NOR_BOOT_CFG
55.globl _start
56_start:
57.globl _NOR_BOOT_CFG
58_NOR_BOOT_CFG:
59	.word	CONFIG_SYS_DV_NOR_BOOT_CFG
60	b	reset
61#else
62.globl _start
63_start:
64	b	reset
65#endif
66#ifdef CONFIG_SPL_BUILD
67/* No exception handlers in preloader */
68	ldr	pc, _hang
69	ldr	pc, _hang
70	ldr	pc, _hang
71	ldr	pc, _hang
72	ldr	pc, _hang
73	ldr	pc, _hang
74	ldr	pc, _hang
75
76_hang:
77	.word	do_hang
78/* pad to 64 byte boundary */
79	.word	0x12345678
80	.word	0x12345678
81	.word	0x12345678
82	.word	0x12345678
83	.word	0x12345678
84	.word	0x12345678
85	.word	0x12345678
86#else
87	ldr	pc, _undefined_instruction
88	ldr	pc, _software_interrupt
89	ldr	pc, _prefetch_abort
90	ldr	pc, _data_abort
91	ldr	pc, _not_used
92	ldr	pc, _irq
93	ldr	pc, _fiq
94
95_undefined_instruction:
96	.word undefined_instruction
97_software_interrupt:
98	.word software_interrupt
99_prefetch_abort:
100	.word prefetch_abort
101_data_abort:
102	.word data_abort
103_not_used:
104	.word not_used
105_irq:
106	.word irq
107_fiq:
108	.word fiq
109
110#endif	/* CONFIG_SPL_BUILD */
111	.balignl 16,0xdeadbeef
112
113
114/*
115 *************************************************************************
116 *
117 * Startup Code (reset vector)
118 *
119 * do important init only if we don't start from memory!
120 * setup Memory and board specific bits prior to relocation.
121 * relocate armboot to ram
122 * setup stack
123 *
124 *************************************************************************
125 */
126
127.globl _TEXT_BASE
128_TEXT_BASE:
129#ifdef CONFIG_NAND_SPL /* deprecated, use instead CONFIG_SPL_BUILD */
130	.word	CONFIG_SYS_TEXT_BASE
131#else
132#ifdef CONFIG_SPL_BUILD
133	.word	CONFIG_SPL_TEXT_BASE
134#else
135	.word	CONFIG_SYS_TEXT_BASE
136#endif
137#endif
138
139/*
140 * These are defined in the board-specific linker script.
141 * Subtracting _start from them lets the linker put their
142 * relative position in the executable instead of leaving
143 * them null.
144 */
145.globl _bss_start_ofs
146_bss_start_ofs:
147	.word __bss_start - _start
148
149.globl _bss_end_ofs
150_bss_end_ofs:
151	.word __bss_end__ - _start
152
153.globl _end_ofs
154_end_ofs:
155	.word _end - _start
156
157#ifdef CONFIG_NAND_U_BOOT
158.globl _end
159_end:
160	.word __bss_end__
161#endif
162
163#ifdef CONFIG_USE_IRQ
164/* IRQ stack memory (calculated at run-time) */
165.globl IRQ_STACK_START
166IRQ_STACK_START:
167	.word	0x0badc0de
168
169/* IRQ stack memory (calculated at run-time) */
170.globl FIQ_STACK_START
171FIQ_STACK_START:
172	.word 0x0badc0de
173#endif
174
175/* IRQ stack memory (calculated at run-time) + 8 bytes */
176.globl IRQ_STACK_START_IN
177IRQ_STACK_START_IN:
178	.word	0x0badc0de
179
180/*
181 * the actual reset code
182 */
183
184reset:
185	/*
186	 * set the cpu to SVC32 mode
187	 */
188	mrs	r0,cpsr
189	bic	r0,r0,#0x1f
190	orr	r0,r0,#0xd3
191	msr	cpsr,r0
192
193	/*
194	 * we do sys-critical inits only at reboot,
195	 * not when booting from ram!
196	 */
197#ifndef CONFIG_SKIP_LOWLEVEL_INIT
198	bl	cpu_init_crit
199#endif
200
201/* Set stackpointer in internal RAM to call board_init_f */
202call_board_init_f:
203#ifdef CONFIG_NAND_SPL /* deprecated, use instead CONFIG_SPL_BUILD */
204	ldr	sp, =(CONFIG_SYS_INIT_SP_ADDR)
205#else
206#ifdef CONFIG_SPL_BUILD
207	ldr	sp, =(CONFIG_SPL_STACK)
208#else
209	ldr	sp, =(CONFIG_SYS_INIT_SP_ADDR)
210#endif
211#endif
212	bic	sp, sp, #7 /* 8-byte alignment for ABI compliance */
213	ldr	r0,=0x00000000
214	bl	board_init_f
215
216/*------------------------------------------------------------------------------*/
217
218/*
219 * void relocate_code (addr_sp, gd, addr_moni)
220 *
221 * This "function" does not return, instead it continues in RAM
222 * after relocating the monitor code.
223 *
224 */
225	.globl	relocate_code
226relocate_code:
227	mov	r4, r0	/* save addr_sp */
228	mov	r5, r1	/* save addr of gd */
229	mov	r6, r2	/* save addr of destination */
230
231	/* Set up the stack						    */
232stack_setup:
233	mov	sp, r4
234
235	adr	r0, _start
236	sub	r9, r6, r0		/* r9 <- relocation offset */
237	cmp	r0, r6
238	beq	clear_bss		/* skip relocation */
239	mov	r1, r6			/* r1 <- scratch for copy loop */
240	ldr	r3, _bss_start_ofs
241	add	r2, r0, r3		/* r2 <- source end address	    */
242
243copy_loop:
244	ldmia	r0!, {r9-r10}		/* copy from source address [r0]    */
245	stmia	r1!, {r9-r10}		/* copy to   target address [r1]    */
246	cmp	r0, r2			/* until source end address [r2]    */
247	blo	copy_loop
248
249#ifndef CONFIG_SPL_BUILD
250	/*
251	 * fix .rel.dyn relocations
252	 */
253	ldr	r0, _TEXT_BASE		/* r0 <- Text base */
254	sub	r9, r6, r0		/* r9 <- relocation offset */
255	ldr	r10, _dynsym_start_ofs	/* r10 <- sym table ofs */
256	add	r10, r10, r0		/* r10 <- sym table in FLASH */
257	ldr	r2, _rel_dyn_start_ofs	/* r2 <- rel dyn start ofs */
258	add	r2, r2, r0		/* r2 <- rel dyn start in FLASH */
259	ldr	r3, _rel_dyn_end_ofs	/* r3 <- rel dyn end ofs */
260	add	r3, r3, r0		/* r3 <- rel dyn end in FLASH */
261fixloop:
262	ldr	r0, [r2]		/* r0 <- location to fix up, IN FLASH! */
263	add	r0, r0, r9		/* r0 <- location to fix up in RAM */
264	ldr	r1, [r2, #4]
265	and	r7, r1, #0xff
266	cmp	r7, #23			/* relative fixup? */
267	beq	fixrel
268	cmp	r7, #2			/* absolute fixup? */
269	beq	fixabs
270	/* ignore unknown type of fixup */
271	b	fixnext
272fixabs:
273	/* absolute fix: set location to (offset) symbol value */
274	mov	r1, r1, LSR #4		/* r1 <- symbol index in .dynsym */
275	add	r1, r10, r1		/* r1 <- address of symbol in table */
276	ldr	r1, [r1, #4]		/* r1 <- symbol value */
277	add	r1, r1, r9		/* r1 <- relocated sym addr */
278	b	fixnext
279fixrel:
280	/* relative fix: increase location by offset */
281	ldr	r1, [r0]
282	add	r1, r1, r9
283fixnext:
284	str	r1, [r0]
285	add	r2, r2, #8		/* each rel.dyn entry is 8 bytes */
286	cmp	r2, r3
287	blo	fixloop
288#endif
289
290clear_bss:
291#ifdef CONFIG_SPL_BUILD
292	/* No relocation for SPL */
293	ldr	r0, =__bss_start
294	ldr	r1, =__bss_end__
295#else
296	ldr	r0, _bss_start_ofs
297	ldr	r1, _bss_end_ofs
298	mov	r4, r6			/* reloc addr */
299	add	r0, r0, r4
300	add	r1, r1, r4
301#endif
302	mov	r2, #0x00000000		/* clear			    */
303
304clbss_l:str	r2, [r0]		/* clear loop...		    */
305	add	r0, r0, #4
306	cmp	r0, r1
307	bne	clbss_l
308
309#ifndef CONFIG_SPL_BUILD
310	bl coloured_LED_init
311	bl red_led_on
312#endif
313
314/*
315 * We are done. Do not return, instead branch to second part of board
316 * initialization, now running from RAM.
317 */
318#ifdef CONFIG_NAND_SPL
319	ldr     r0, _nand_boot_ofs
320	mov	pc, r0
321
322_nand_boot_ofs:
323	.word nand_boot
324#else
325	ldr	r0, _board_init_r_ofs
326	ldr	r1, _TEXT_BASE
327	add	lr, r0, r1
328	add	lr, lr, r9
329	/* setup parameters for board_init_r */
330	mov	r0, r5		/* gd_t */
331	mov	r1, r6		/* dest_addr */
332	/* jump to it ... */
333	mov	pc, lr
334
335_board_init_r_ofs:
336	.word board_init_r - _start
337#endif
338
339_rel_dyn_start_ofs:
340	.word __rel_dyn_start - _start
341_rel_dyn_end_ofs:
342	.word __rel_dyn_end - _start
343_dynsym_start_ofs:
344	.word __dynsym_start - _start
345
346/*
347 *************************************************************************
348 *
349 * CPU_init_critical registers
350 *
351 * setup important registers
352 * setup memory timing
353 *
354 *************************************************************************
355 */
356#ifndef CONFIG_SKIP_LOWLEVEL_INIT
357cpu_init_crit:
358	/*
359	 * flush v4 I/D caches
360	 */
361	mov	r0, #0
362	mcr	p15, 0, r0, c7, c7, 0	/* flush v3/v4 cache */
363	mcr	p15, 0, r0, c8, c7, 0	/* flush v4 TLB */
364
365	/*
366	 * disable MMU stuff and caches
367	 */
368	mrc	p15, 0, r0, c1, c0, 0
369	bic	r0, r0, #0x00002300	/* clear bits 13, 9:8 (--V- --RS) */
370	bic	r0, r0, #0x00000087	/* clear bits 7, 2:0 (B--- -CAM) */
371	orr	r0, r0, #0x00000002	/* set bit 2 (A) Align */
372	orr	r0, r0, #0x00001000	/* set bit 12 (I) I-Cache */
373	mcr	p15, 0, r0, c1, c0, 0
374
375	/*
376	 * Go setup Memory and board specific bits prior to relocation.
377	 */
378	mov	ip, lr		/* perserve link reg across call */
379	bl	lowlevel_init	/* go setup pll,mux,memory */
380	mov	lr, ip		/* restore link */
381	mov	pc, lr		/* back to my caller */
382#endif /* CONFIG_SKIP_LOWLEVEL_INIT */
383
384#ifndef CONFIG_SPL_BUILD
385/*
386 *************************************************************************
387 *
388 * Interrupt handling
389 *
390 *************************************************************************
391 */
392
393@
394@ IRQ stack frame.
395@
396#define S_FRAME_SIZE	72
397
398#define S_OLD_R0	68
399#define S_PSR		64
400#define S_PC		60
401#define S_LR		56
402#define S_SP		52
403
404#define S_IP		48
405#define S_FP		44
406#define S_R10		40
407#define S_R9		36
408#define S_R8		32
409#define S_R7		28
410#define S_R6		24
411#define S_R5		20
412#define S_R4		16
413#define S_R3		12
414#define S_R2		8
415#define S_R1		4
416#define S_R0		0
417
418#define MODE_SVC 0x13
419#define I_BIT	 0x80
420
421/*
422 * use bad_save_user_regs for abort/prefetch/undef/swi ...
423 * use irq_save_user_regs / irq_restore_user_regs for IRQ/FIQ handling
424 */
425
426	.macro	bad_save_user_regs
427	@ carve out a frame on current user stack
428	sub	sp, sp, #S_FRAME_SIZE
429	stmia	sp, {r0 - r12}	@ Save user registers (now in svc mode) r0-r12
430	ldr	r2, IRQ_STACK_START_IN
431	@ get values for "aborted" pc and cpsr (into parm regs)
432	ldmia	r2, {r2 - r3}
433	add	r0, sp, #S_FRAME_SIZE		@ grab pointer to old stack
434	add	r5, sp, #S_SP
435	mov	r1, lr
436	stmia	r5, {r0 - r3}	@ save sp_SVC, lr_SVC, pc, cpsr
437	mov	r0, sp		@ save current stack into r0 (param register)
438	.endm
439
440	.macro	irq_save_user_regs
441	sub	sp, sp, #S_FRAME_SIZE
442	stmia	sp, {r0 - r12}			@ Calling r0-r12
443	@ !!!! R8 NEEDS to be saved !!!! a reserved stack spot would be good.
444	add	r8, sp, #S_PC
445	stmdb	r8, {sp, lr}^		@ Calling SP, LR
446	str	lr, [r8, #0]		@ Save calling PC
447	mrs	r6, spsr
448	str	r6, [r8, #4]		@ Save CPSR
449	str	r0, [r8, #8]		@ Save OLD_R0
450	mov	r0, sp
451	.endm
452
453	.macro	irq_restore_user_regs
454	ldmia	sp, {r0 - lr}^			@ Calling r0 - lr
455	mov	r0, r0
456	ldr	lr, [sp, #S_PC]			@ Get PC
457	add	sp, sp, #S_FRAME_SIZE
458	subs	pc, lr, #4		@ return & move spsr_svc into cpsr
459	.endm
460
461	.macro get_bad_stack
462	ldr	r13, IRQ_STACK_START_IN		@ setup our mode stack
463
464	str	lr, [r13]	@ save caller lr in position 0 of saved stack
465	mrs	lr, spsr	@ get the spsr
466	str	lr, [r13, #4]	@ save spsr in position 1 of saved stack
467	mov	r13, #MODE_SVC	@ prepare SVC-Mode
468	@ msr	spsr_c, r13
469	msr	spsr, r13	@ switch modes, make sure moves will execute
470	mov	lr, pc		@ capture return pc
471	movs	pc, lr		@ jump to next instruction & switch modes.
472	.endm
473
474	.macro get_irq_stack			@ setup IRQ stack
475	ldr	sp, IRQ_STACK_START
476	.endm
477
478	.macro get_fiq_stack			@ setup FIQ stack
479	ldr	sp, FIQ_STACK_START
480	.endm
481#endif	/* CONFIG_SPL_BUILD */
482
483/*
484 * exception handlers
485 */
486#ifdef CONFIG_SPL_BUILD
487	.align	5
488do_hang:
489	ldr	sp, _TEXT_BASE			/* switch to abort stack */
4901:
491	bl	1b				/* hang and never return */
492#else	/* !CONFIG_SPL_BUILD */
493	.align  5
494undefined_instruction:
495	get_bad_stack
496	bad_save_user_regs
497	bl	do_undefined_instruction
498
499	.align	5
500software_interrupt:
501	get_bad_stack
502	bad_save_user_regs
503	bl	do_software_interrupt
504
505	.align	5
506prefetch_abort:
507	get_bad_stack
508	bad_save_user_regs
509	bl	do_prefetch_abort
510
511	.align	5
512data_abort:
513	get_bad_stack
514	bad_save_user_regs
515	bl	do_data_abort
516
517	.align	5
518not_used:
519	get_bad_stack
520	bad_save_user_regs
521	bl	do_not_used
522
523#ifdef CONFIG_USE_IRQ
524
525	.align	5
526irq:
527	get_irq_stack
528	irq_save_user_regs
529	bl	do_irq
530	irq_restore_user_regs
531
532	.align	5
533fiq:
534	get_fiq_stack
535	/* someone ought to write a more effiction fiq_save_user_regs */
536	irq_save_user_regs
537	bl	do_fiq
538	irq_restore_user_regs
539
540#else
541
542	.align	5
543irq:
544	get_bad_stack
545	bad_save_user_regs
546	bl	do_irq
547
548	.align	5
549fiq:
550	get_bad_stack
551	bad_save_user_regs
552	bl	do_fiq
553
554#endif
555#endif	/* CONFIG_SPL_BUILD */
556