xref: /openbmc/u-boot/arch/arm/cpu/arm926ejs/start.S (revision bf48fcb6) 
1/*
2 *  armboot - Startup Code for ARM926EJS CPU-core
3 *
4 *  Copyright (c) 2003  Texas Instruments
5 *
6 *  ----- Adapted for OMAP1610 OMAP730 from ARM925t code ------
7 *
8 *  Copyright (c) 2001	Marius Gröger <mag@sysgo.de>
9 *  Copyright (c) 2002	Alex Züpke <azu@sysgo.de>
10 *  Copyright (c) 2002	Gary Jennejohn <garyj@denx.de>
11 *  Copyright (c) 2003	Richard Woodruff <r-woodruff2@ti.com>
12 *  Copyright (c) 2003	Kshitij <kshitij@ti.com>
13 *  Copyright (c) 2010	Albert Aribaud <albert.u.boot@aribaud.net>
14 *
15 * See file CREDITS for list of people who contributed to this
16 * project.
17 *
18 * This program is free software; you can redistribute it and/or
19 * modify it under the terms of the GNU General Public License as
20 * published by the Free Software Foundation; either version 2 of
21 * the License, or (at your option) any later version.
22 *
23 * This program is distributed in the hope that it will be useful,
24 * but WITHOUT ANY WARRANTY; without even the implied warranty of
25 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
26 * GNU General Public License for more details.
27 *
28 * You should have received a copy of the GNU General Public License
29 * along with this program; if not, write to the Free Software
30 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
31 * MA 02111-1307 USA
32 */
33
34#include <asm-offsets.h>
35#include <config.h>
36#include <common.h>
37#include <version.h>
38
39/*
40 *************************************************************************
41 *
42 * Jump vector table as in table 3.1 in [1]
43 *
44 *************************************************************************
45 */
46
47
48#ifdef CONFIG_SYS_DV_NOR_BOOT_CFG
49.globl _start
50_start:
51.globl _NOR_BOOT_CFG
52_NOR_BOOT_CFG:
53	.word	CONFIG_SYS_DV_NOR_BOOT_CFG
54	b	reset
55#else
56.globl _start
57_start:
58	b	reset
59#endif
60#ifdef CONFIG_SPL_BUILD
61/* No exception handlers in preloader */
62	ldr	pc, _hang
63	ldr	pc, _hang
64	ldr	pc, _hang
65	ldr	pc, _hang
66	ldr	pc, _hang
67	ldr	pc, _hang
68	ldr	pc, _hang
69
70_hang:
71	.word	do_hang
72/* pad to 64 byte boundary */
73	.word	0x12345678
74	.word	0x12345678
75	.word	0x12345678
76	.word	0x12345678
77	.word	0x12345678
78	.word	0x12345678
79	.word	0x12345678
80#else
81	ldr	pc, _undefined_instruction
82	ldr	pc, _software_interrupt
83	ldr	pc, _prefetch_abort
84	ldr	pc, _data_abort
85	ldr	pc, _not_used
86	ldr	pc, _irq
87	ldr	pc, _fiq
88
89_undefined_instruction:
90	.word undefined_instruction
91_software_interrupt:
92	.word software_interrupt
93_prefetch_abort:
94	.word prefetch_abort
95_data_abort:
96	.word data_abort
97_not_used:
98	.word not_used
99_irq:
100	.word irq
101_fiq:
102	.word fiq
103
104#endif	/* CONFIG_SPL_BUILD */
105	.balignl 16,0xdeadbeef
106
107
108/*
109 *************************************************************************
110 *
111 * Startup Code (reset vector)
112 *
113 * do important init only if we don't start from memory!
114 * setup Memory and board specific bits prior to relocation.
115 * relocate armboot to ram
116 * setup stack
117 *
118 *************************************************************************
119 */
120
121.globl _TEXT_BASE
122_TEXT_BASE:
123#ifdef CONFIG_NAND_SPL /* deprecated, use instead CONFIG_SPL_BUILD */
124	.word	CONFIG_SYS_TEXT_BASE
125#else
126#ifdef CONFIG_SPL_BUILD
127	.word	CONFIG_SPL_TEXT_BASE
128#else
129	.word	CONFIG_SYS_TEXT_BASE
130#endif
131#endif
132
133/*
134 * These are defined in the board-specific linker script.
135 * Subtracting _start from them lets the linker put their
136 * relative position in the executable instead of leaving
137 * them null.
138 */
139.globl _bss_start_ofs
140_bss_start_ofs:
141	.word __bss_start - _start
142
143.globl _bss_end_ofs
144_bss_end_ofs:
145	.word __bss_end__ - _start
146
147.globl _end_ofs
148_end_ofs:
149	.word _end - _start
150
151#ifdef CONFIG_NAND_U_BOOT
152.globl _end
153_end:
154	.word __bss_end__
155#endif
156
157#ifdef CONFIG_USE_IRQ
158/* IRQ stack memory (calculated at run-time) */
159.globl IRQ_STACK_START
160IRQ_STACK_START:
161	.word	0x0badc0de
162
163/* IRQ stack memory (calculated at run-time) */
164.globl FIQ_STACK_START
165FIQ_STACK_START:
166	.word 0x0badc0de
167#endif
168
169/* IRQ stack memory (calculated at run-time) + 8 bytes */
170.globl IRQ_STACK_START_IN
171IRQ_STACK_START_IN:
172	.word	0x0badc0de
173
174/*
175 * the actual reset code
176 */
177
178reset:
179	/*
180	 * set the cpu to SVC32 mode
181	 */
182	mrs	r0,cpsr
183	bic	r0,r0,#0x1f
184	orr	r0,r0,#0xd3
185	msr	cpsr,r0
186
187	/*
188	 * we do sys-critical inits only at reboot,
189	 * not when booting from ram!
190	 */
191#ifndef CONFIG_SKIP_LOWLEVEL_INIT
192	bl	cpu_init_crit
193#endif
194
195	bl	_main
196
197/*------------------------------------------------------------------------------*/
198
199#if !defined(CONFIG_SPL_BUILD) || defined(CONFIG_NAND_SPL)
200/*
201 * void relocate_code (addr_sp, gd, addr_moni)
202 *
203 * This "function" does not return, instead it continues in RAM
204 * after relocating the monitor code.
205 *
206 */
207	.globl	relocate_code
208relocate_code:
209	mov	r4, r0	/* save addr_sp */
210	mov	r5, r1	/* save addr of gd */
211	mov	r6, r2	/* save addr of destination */
212
213	adr	r0, _start
214	sub	r9, r6, r0		/* r9 <- relocation offset */
215	cmp	r0, r6
216	moveq	r9, #0			/* no relocation. offset(r9) = 0 */
217	beq	relocate_done		/* skip relocation */
218	mov	r1, r6			/* r1 <- scratch for copy loop */
219	ldr	r3, _bss_start_ofs
220	add	r2, r0, r3		/* r2 <- source end address	    */
221
222copy_loop:
223	ldmia	r0!, {r9-r10}		/* copy from source address [r0]    */
224	stmia	r1!, {r9-r10}		/* copy to   target address [r1]    */
225	cmp	r0, r2			/* until source end address [r2]    */
226	blo	copy_loop
227
228#ifndef CONFIG_SPL_BUILD
229	/*
230	 * fix .rel.dyn relocations
231	 */
232	ldr	r0, _TEXT_BASE		/* r0 <- Text base */
233	sub	r9, r6, r0		/* r9 <- relocation offset */
234	ldr	r10, _dynsym_start_ofs	/* r10 <- sym table ofs */
235	add	r10, r10, r0		/* r10 <- sym table in FLASH */
236	ldr	r2, _rel_dyn_start_ofs	/* r2 <- rel dyn start ofs */
237	add	r2, r2, r0		/* r2 <- rel dyn start in FLASH */
238	ldr	r3, _rel_dyn_end_ofs	/* r3 <- rel dyn end ofs */
239	add	r3, r3, r0		/* r3 <- rel dyn end in FLASH */
240fixloop:
241	ldr	r0, [r2]		/* r0 <- location to fix up, IN FLASH! */
242	add	r0, r0, r9		/* r0 <- location to fix up in RAM */
243	ldr	r1, [r2, #4]
244	and	r7, r1, #0xff
245	cmp	r7, #23			/* relative fixup? */
246	beq	fixrel
247	cmp	r7, #2			/* absolute fixup? */
248	beq	fixabs
249	/* ignore unknown type of fixup */
250	b	fixnext
251fixabs:
252	/* absolute fix: set location to (offset) symbol value */
253	mov	r1, r1, LSR #4		/* r1 <- symbol index in .dynsym */
254	add	r1, r10, r1		/* r1 <- address of symbol in table */
255	ldr	r1, [r1, #4]		/* r1 <- symbol value */
256	add	r1, r1, r9		/* r1 <- relocated sym addr */
257	b	fixnext
258fixrel:
259	/* relative fix: increase location by offset */
260	ldr	r1, [r0]
261	add	r1, r1, r9
262fixnext:
263	str	r1, [r0]
264	add	r2, r2, #8		/* each rel.dyn entry is 8 bytes */
265	cmp	r2, r3
266	blo	fixloop
267#endif
268
269relocate_done:
270
271	bx	lr
272
273_rel_dyn_start_ofs:
274	.word __rel_dyn_start - _start
275_rel_dyn_end_ofs:
276	.word __rel_dyn_end - _start
277_dynsym_start_ofs:
278	.word __dynsym_start - _start
279
280#endif
281
282	.globl	c_runtime_cpu_setup
283c_runtime_cpu_setup:
284
285	bx	lr
286
287/*
288 *************************************************************************
289 *
290 * CPU_init_critical registers
291 *
292 * setup important registers
293 * setup memory timing
294 *
295 *************************************************************************
296 */
297#ifndef CONFIG_SKIP_LOWLEVEL_INIT
298cpu_init_crit:
299	/*
300	 * flush D cache before disabling it
301	 */
302	mov	r0, #0
303flush_dcache:
304	mrc	p15, 0, r15, c7, c10, 3
305	bne	flush_dcache
306
307	mcr	p15, 0, r0, c8, c7, 0	/* invalidate TLB */
308	mcr	p15, 0, r0, c7, c5, 0	/* invalidate I Cache */
309
310	/*
311	 * disable MMU and D cache
312	 * enable I cache if CONFIG_SYS_ICACHE_OFF is not defined
313	 */
314	mrc	p15, 0, r0, c1, c0, 0
315	bic	r0, r0, #0x00000300	/* clear bits 9:8 (---- --RS) */
316	bic	r0, r0, #0x00000087	/* clear bits 7, 2:0 (B--- -CAM) */
317#ifdef CONFIG_SYS_EXCEPTION_VECTORS_HIGH
318	orr	r0, r0, #0x00002000	/* set bit 13 (--V- ----) */
319#else
320	bic	r0, r0, #0x00002000	/* clear bit 13 (--V- ----) */
321#endif
322	orr	r0, r0, #0x00000002	/* set bit 2 (A) Align */
323#ifndef CONFIG_SYS_ICACHE_OFF
324	orr	r0, r0, #0x00001000	/* set bit 12 (I) I-Cache */
325#endif
326	mcr	p15, 0, r0, c1, c0, 0
327
328	/*
329	 * Go setup Memory and board specific bits prior to relocation.
330	 */
331	mov	ip, lr		/* perserve link reg across call */
332	bl	lowlevel_init	/* go setup pll,mux,memory */
333	mov	lr, ip		/* restore link */
334	mov	pc, lr		/* back to my caller */
335#endif /* CONFIG_SKIP_LOWLEVEL_INIT */
336
337#ifndef CONFIG_SPL_BUILD
338/*
339 *************************************************************************
340 *
341 * Interrupt handling
342 *
343 *************************************************************************
344 */
345
346@
347@ IRQ stack frame.
348@
349#define S_FRAME_SIZE	72
350
351#define S_OLD_R0	68
352#define S_PSR		64
353#define S_PC		60
354#define S_LR		56
355#define S_SP		52
356
357#define S_IP		48
358#define S_FP		44
359#define S_R10		40
360#define S_R9		36
361#define S_R8		32
362#define S_R7		28
363#define S_R6		24
364#define S_R5		20
365#define S_R4		16
366#define S_R3		12
367#define S_R2		8
368#define S_R1		4
369#define S_R0		0
370
371#define MODE_SVC 0x13
372#define I_BIT	 0x80
373
374/*
375 * use bad_save_user_regs for abort/prefetch/undef/swi ...
376 * use irq_save_user_regs / irq_restore_user_regs for IRQ/FIQ handling
377 */
378
379	.macro	bad_save_user_regs
380	@ carve out a frame on current user stack
381	sub	sp, sp, #S_FRAME_SIZE
382	stmia	sp, {r0 - r12}	@ Save user registers (now in svc mode) r0-r12
383	ldr	r2, IRQ_STACK_START_IN
384	@ get values for "aborted" pc and cpsr (into parm regs)
385	ldmia	r2, {r2 - r3}
386	add	r0, sp, #S_FRAME_SIZE		@ grab pointer to old stack
387	add	r5, sp, #S_SP
388	mov	r1, lr
389	stmia	r5, {r0 - r3}	@ save sp_SVC, lr_SVC, pc, cpsr
390	mov	r0, sp		@ save current stack into r0 (param register)
391	.endm
392
393	.macro	irq_save_user_regs
394	sub	sp, sp, #S_FRAME_SIZE
395	stmia	sp, {r0 - r12}			@ Calling r0-r12
396	@ !!!! R8 NEEDS to be saved !!!! a reserved stack spot would be good.
397	add	r8, sp, #S_PC
398	stmdb	r8, {sp, lr}^		@ Calling SP, LR
399	str	lr, [r8, #0]		@ Save calling PC
400	mrs	r6, spsr
401	str	r6, [r8, #4]		@ Save CPSR
402	str	r0, [r8, #8]		@ Save OLD_R0
403	mov	r0, sp
404	.endm
405
406	.macro	irq_restore_user_regs
407	ldmia	sp, {r0 - lr}^			@ Calling r0 - lr
408	mov	r0, r0
409	ldr	lr, [sp, #S_PC]			@ Get PC
410	add	sp, sp, #S_FRAME_SIZE
411	subs	pc, lr, #4		@ return & move spsr_svc into cpsr
412	.endm
413
414	.macro get_bad_stack
415	ldr	r13, IRQ_STACK_START_IN		@ setup our mode stack
416
417	str	lr, [r13]	@ save caller lr in position 0 of saved stack
418	mrs	lr, spsr	@ get the spsr
419	str	lr, [r13, #4]	@ save spsr in position 1 of saved stack
420	mov	r13, #MODE_SVC	@ prepare SVC-Mode
421	@ msr	spsr_c, r13
422	msr	spsr, r13	@ switch modes, make sure moves will execute
423	mov	lr, pc		@ capture return pc
424	movs	pc, lr		@ jump to next instruction & switch modes.
425	.endm
426
427	.macro get_irq_stack			@ setup IRQ stack
428	ldr	sp, IRQ_STACK_START
429	.endm
430
431	.macro get_fiq_stack			@ setup FIQ stack
432	ldr	sp, FIQ_STACK_START
433	.endm
434#endif	/* CONFIG_SPL_BUILD */
435
436/*
437 * exception handlers
438 */
439#ifdef CONFIG_SPL_BUILD
440	.align	5
441do_hang:
442	ldr	sp, _TEXT_BASE			/* switch to abort stack */
4431:
444	bl	1b				/* hang and never return */
445#else	/* !CONFIG_SPL_BUILD */
446	.align  5
447undefined_instruction:
448	get_bad_stack
449	bad_save_user_regs
450	bl	do_undefined_instruction
451
452	.align	5
453software_interrupt:
454	get_bad_stack
455	bad_save_user_regs
456	bl	do_software_interrupt
457
458	.align	5
459prefetch_abort:
460	get_bad_stack
461	bad_save_user_regs
462	bl	do_prefetch_abort
463
464	.align	5
465data_abort:
466	get_bad_stack
467	bad_save_user_regs
468	bl	do_data_abort
469
470	.align	5
471not_used:
472	get_bad_stack
473	bad_save_user_regs
474	bl	do_not_used
475
476#ifdef CONFIG_USE_IRQ
477
478	.align	5
479irq:
480	get_irq_stack
481	irq_save_user_regs
482	bl	do_irq
483	irq_restore_user_regs
484
485	.align	5
486fiq:
487	get_fiq_stack
488	/* someone ought to write a more effiction fiq_save_user_regs */
489	irq_save_user_regs
490	bl	do_fiq
491	irq_restore_user_regs
492
493#else
494
495	.align	5
496irq:
497	get_bad_stack
498	bad_save_user_regs
499	bl	do_irq
500
501	.align	5
502fiq:
503	get_bad_stack
504	bad_save_user_regs
505	bl	do_fiq
506
507#endif
508#endif	/* CONFIG_SPL_BUILD */
509