xref: /openbmc/u-boot/arch/arm/cpu/arm926ejs/start.S (revision b1e6c4c3) 
1/*
2 *  armboot - Startup Code for ARM926EJS CPU-core
3 *
4 *  Copyright (c) 2003  Texas Instruments
5 *
6 *  ----- Adapted for OMAP1610 OMAP730 from ARM925t code ------
7 *
8 *  Copyright (c) 2001	Marius Gröger <mag@sysgo.de>
9 *  Copyright (c) 2002	Alex Züpke <azu@sysgo.de>
10 *  Copyright (c) 2002	Gary Jennejohn <garyj@denx.de>
11 *  Copyright (c) 2003	Richard Woodruff <r-woodruff2@ti.com>
12 *  Copyright (c) 2003	Kshitij <kshitij@ti.com>
13 *  Copyright (c) 2010	Albert Aribaud <albert.u.boot@aribaud.net>
14 *
15 * See file CREDITS for list of people who contributed to this
16 * project.
17 *
18 * This program is free software; you can redistribute it and/or
19 * modify it under the terms of the GNU General Public License as
20 * published by the Free Software Foundation; either version 2 of
21 * the License, or (at your option) any later version.
22 *
23 * This program is distributed in the hope that it will be useful,
24 * but WITHOUT ANY WARRANTY; without even the implied warranty of
25 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
26 * GNU General Public License for more details.
27 *
28 * You should have received a copy of the GNU General Public License
29 * along with this program; if not, write to the Free Software
30 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
31 * MA 02111-1307 USA
32 */
33
34#include <asm-offsets.h>
35#include <config.h>
36#include <common.h>
37#include <version.h>
38
39/*
40 *************************************************************************
41 *
42 * Jump vector table as in table 3.1 in [1]
43 *
44 *************************************************************************
45 */
46
47
48#ifdef CONFIG_SYS_DV_NOR_BOOT_CFG
49.globl _start
50_start:
51.globl _NOR_BOOT_CFG
52_NOR_BOOT_CFG:
53	.word	CONFIG_SYS_DV_NOR_BOOT_CFG
54	b	reset
55#else
56.globl _start
57_start:
58	b	reset
59#endif
60#ifdef CONFIG_SPL_BUILD
61/* No exception handlers in preloader */
62	ldr	pc, _hang
63	ldr	pc, _hang
64	ldr	pc, _hang
65	ldr	pc, _hang
66	ldr	pc, _hang
67	ldr	pc, _hang
68	ldr	pc, _hang
69
70_hang:
71	.word	do_hang
72/* pad to 64 byte boundary */
73	.word	0x12345678
74	.word	0x12345678
75	.word	0x12345678
76	.word	0x12345678
77	.word	0x12345678
78	.word	0x12345678
79	.word	0x12345678
80#else
81	ldr	pc, _undefined_instruction
82	ldr	pc, _software_interrupt
83	ldr	pc, _prefetch_abort
84	ldr	pc, _data_abort
85	ldr	pc, _not_used
86	ldr	pc, _irq
87	ldr	pc, _fiq
88
89_undefined_instruction:
90	.word undefined_instruction
91_software_interrupt:
92	.word software_interrupt
93_prefetch_abort:
94	.word prefetch_abort
95_data_abort:
96	.word data_abort
97_not_used:
98	.word not_used
99_irq:
100	.word irq
101_fiq:
102	.word fiq
103
104#endif	/* CONFIG_SPL_BUILD */
105	.balignl 16,0xdeadbeef
106
107
108/*
109 *************************************************************************
110 *
111 * Startup Code (reset vector)
112 *
113 * do important init only if we don't start from memory!
114 * setup Memory and board specific bits prior to relocation.
115 * relocate armboot to ram
116 * setup stack
117 *
118 *************************************************************************
119 */
120
121.globl _TEXT_BASE
122_TEXT_BASE:
123#if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_TEXT_BASE)
124	.word	CONFIG_SPL_TEXT_BASE
125#else
126	.word	CONFIG_SYS_TEXT_BASE
127#endif
128
129/*
130 * These are defined in the board-specific linker script.
131 * Subtracting _start from them lets the linker put their
132 * relative position in the executable instead of leaving
133 * them null.
134 */
135.globl _bss_start_ofs
136_bss_start_ofs:
137	.word __bss_start - _start
138
139.globl _image_copy_end_ofs
140_image_copy_end_ofs:
141	.word __image_copy_end - _start
142
143.globl _bss_end_ofs
144_bss_end_ofs:
145	.word __bss_end - _start
146
147.globl _end_ofs
148_end_ofs:
149	.word _end - _start
150
151#ifdef CONFIG_USE_IRQ
152/* IRQ stack memory (calculated at run-time) */
153.globl IRQ_STACK_START
154IRQ_STACK_START:
155	.word	0x0badc0de
156
157/* IRQ stack memory (calculated at run-time) */
158.globl FIQ_STACK_START
159FIQ_STACK_START:
160	.word 0x0badc0de
161#endif
162
163/* IRQ stack memory (calculated at run-time) + 8 bytes */
164.globl IRQ_STACK_START_IN
165IRQ_STACK_START_IN:
166	.word	0x0badc0de
167
168/*
169 * the actual reset code
170 */
171
172reset:
173	/*
174	 * set the cpu to SVC32 mode
175	 */
176	mrs	r0,cpsr
177	bic	r0,r0,#0x1f
178	orr	r0,r0,#0xd3
179	msr	cpsr,r0
180
181	/*
182	 * we do sys-critical inits only at reboot,
183	 * not when booting from ram!
184	 */
185#ifndef CONFIG_SKIP_LOWLEVEL_INIT
186	bl	cpu_init_crit
187#endif
188
189	bl	_main
190
191/*------------------------------------------------------------------------------*/
192
193/*
194 * void relocate_code(addr_moni)
195 *
196 * This function relocates the monitor code.
197 */
198	.globl	relocate_code
199relocate_code:
200	mov	r6, r0	/* save addr of destination */
201
202	adr	r0, _start
203	subs	r9, r6, r0		/* r9 <- relocation offset */
204	beq	relocate_done		/* skip relocation */
205	mov	r1, r6			/* r1 <- scratch for copy loop */
206	ldr	r3, _image_copy_end_ofs
207	add	r2, r0, r3		/* r2 <- source end address	    */
208
209copy_loop:
210	ldmia	r0!, {r10-r11}		/* copy from source address [r0]    */
211	stmia	r1!, {r10-r11}		/* copy to   target address [r1]    */
212	cmp	r0, r2			/* until source end address [r2]    */
213	blo	copy_loop
214
215#ifndef CONFIG_SPL_BUILD
216	/*
217	 * fix .rel.dyn relocations
218	 */
219	ldr	r0, _TEXT_BASE		/* r0 <- Text base */
220	ldr	r10, _dynsym_start_ofs	/* r10 <- sym table ofs */
221	add	r10, r10, r0		/* r10 <- sym table in FLASH */
222	ldr	r2, _rel_dyn_start_ofs	/* r2 <- rel dyn start ofs */
223	add	r2, r2, r0		/* r2 <- rel dyn start in FLASH */
224	ldr	r3, _rel_dyn_end_ofs	/* r3 <- rel dyn end ofs */
225	add	r3, r3, r0		/* r3 <- rel dyn end in FLASH */
226fixloop:
227	ldr	r0, [r2]		/* r0 <- location to fix up, IN FLASH! */
228	add	r0, r0, r9		/* r0 <- location to fix up in RAM */
229	ldr	r1, [r2, #4]
230	and	r7, r1, #0xff
231	cmp	r7, #23			/* relative fixup? */
232	beq	fixrel
233	cmp	r7, #2			/* absolute fixup? */
234	beq	fixabs
235	/* ignore unknown type of fixup */
236	b	fixnext
237fixabs:
238	/* absolute fix: set location to (offset) symbol value */
239	mov	r1, r1, LSR #4		/* r1 <- symbol index in .dynsym */
240	add	r1, r10, r1		/* r1 <- address of symbol in table */
241	ldr	r1, [r1, #4]		/* r1 <- symbol value */
242	add	r1, r1, r9		/* r1 <- relocated sym addr */
243	b	fixnext
244fixrel:
245	/* relative fix: increase location by offset */
246	ldr	r1, [r0]
247	add	r1, r1, r9
248fixnext:
249	str	r1, [r0]
250	add	r2, r2, #8		/* each rel.dyn entry is 8 bytes */
251	cmp	r2, r3
252	blo	fixloop
253#endif
254
255relocate_done:
256
257	bx	lr
258
259#ifndef CONFIG_SPL_BUILD
260
261_rel_dyn_start_ofs:
262	.word __rel_dyn_start - _start
263_rel_dyn_end_ofs:
264	.word __rel_dyn_end - _start
265_dynsym_start_ofs:
266	.word __dynsym_start - _start
267
268#endif
269
270	.globl	c_runtime_cpu_setup
271c_runtime_cpu_setup:
272
273	bx	lr
274
275/*
276 *************************************************************************
277 *
278 * CPU_init_critical registers
279 *
280 * setup important registers
281 * setup memory timing
282 *
283 *************************************************************************
284 */
285#ifndef CONFIG_SKIP_LOWLEVEL_INIT
286cpu_init_crit:
287	/*
288	 * flush D cache before disabling it
289	 */
290	mov	r0, #0
291flush_dcache:
292	mrc	p15, 0, r15, c7, c10, 3
293	bne	flush_dcache
294
295	mcr	p15, 0, r0, c8, c7, 0	/* invalidate TLB */
296	mcr	p15, 0, r0, c7, c5, 0	/* invalidate I Cache */
297
298	/*
299	 * disable MMU and D cache
300	 * enable I cache if CONFIG_SYS_ICACHE_OFF is not defined
301	 */
302	mrc	p15, 0, r0, c1, c0, 0
303	bic	r0, r0, #0x00000300	/* clear bits 9:8 (---- --RS) */
304	bic	r0, r0, #0x00000087	/* clear bits 7, 2:0 (B--- -CAM) */
305#ifdef CONFIG_SYS_EXCEPTION_VECTORS_HIGH
306	orr	r0, r0, #0x00002000	/* set bit 13 (--V- ----) */
307#else
308	bic	r0, r0, #0x00002000	/* clear bit 13 (--V- ----) */
309#endif
310	orr	r0, r0, #0x00000002	/* set bit 2 (A) Align */
311#ifndef CONFIG_SYS_ICACHE_OFF
312	orr	r0, r0, #0x00001000	/* set bit 12 (I) I-Cache */
313#endif
314	mcr	p15, 0, r0, c1, c0, 0
315
316	/*
317	 * Go setup Memory and board specific bits prior to relocation.
318	 */
319	mov	ip, lr		/* perserve link reg across call */
320	bl	lowlevel_init	/* go setup pll,mux,memory */
321	mov	lr, ip		/* restore link */
322	mov	pc, lr		/* back to my caller */
323#endif /* CONFIG_SKIP_LOWLEVEL_INIT */
324
325#ifndef CONFIG_SPL_BUILD
326/*
327 *************************************************************************
328 *
329 * Interrupt handling
330 *
331 *************************************************************************
332 */
333
334@
335@ IRQ stack frame.
336@
337#define S_FRAME_SIZE	72
338
339#define S_OLD_R0	68
340#define S_PSR		64
341#define S_PC		60
342#define S_LR		56
343#define S_SP		52
344
345#define S_IP		48
346#define S_FP		44
347#define S_R10		40
348#define S_R9		36
349#define S_R8		32
350#define S_R7		28
351#define S_R6		24
352#define S_R5		20
353#define S_R4		16
354#define S_R3		12
355#define S_R2		8
356#define S_R1		4
357#define S_R0		0
358
359#define MODE_SVC 0x13
360#define I_BIT	 0x80
361
362/*
363 * use bad_save_user_regs for abort/prefetch/undef/swi ...
364 * use irq_save_user_regs / irq_restore_user_regs for IRQ/FIQ handling
365 */
366
367	.macro	bad_save_user_regs
368	@ carve out a frame on current user stack
369	sub	sp, sp, #S_FRAME_SIZE
370	stmia	sp, {r0 - r12}	@ Save user registers (now in svc mode) r0-r12
371	ldr	r2, IRQ_STACK_START_IN
372	@ get values for "aborted" pc and cpsr (into parm regs)
373	ldmia	r2, {r2 - r3}
374	add	r0, sp, #S_FRAME_SIZE		@ grab pointer to old stack
375	add	r5, sp, #S_SP
376	mov	r1, lr
377	stmia	r5, {r0 - r3}	@ save sp_SVC, lr_SVC, pc, cpsr
378	mov	r0, sp		@ save current stack into r0 (param register)
379	.endm
380
381	.macro	irq_save_user_regs
382	sub	sp, sp, #S_FRAME_SIZE
383	stmia	sp, {r0 - r12}			@ Calling r0-r12
384	@ !!!! R8 NEEDS to be saved !!!! a reserved stack spot would be good.
385	add	r8, sp, #S_PC
386	stmdb	r8, {sp, lr}^		@ Calling SP, LR
387	str	lr, [r8, #0]		@ Save calling PC
388	mrs	r6, spsr
389	str	r6, [r8, #4]		@ Save CPSR
390	str	r0, [r8, #8]		@ Save OLD_R0
391	mov	r0, sp
392	.endm
393
394	.macro	irq_restore_user_regs
395	ldmia	sp, {r0 - lr}^			@ Calling r0 - lr
396	mov	r0, r0
397	ldr	lr, [sp, #S_PC]			@ Get PC
398	add	sp, sp, #S_FRAME_SIZE
399	subs	pc, lr, #4		@ return & move spsr_svc into cpsr
400	.endm
401
402	.macro get_bad_stack
403	ldr	r13, IRQ_STACK_START_IN		@ setup our mode stack
404
405	str	lr, [r13]	@ save caller lr in position 0 of saved stack
406	mrs	lr, spsr	@ get the spsr
407	str	lr, [r13, #4]	@ save spsr in position 1 of saved stack
408	mov	r13, #MODE_SVC	@ prepare SVC-Mode
409	@ msr	spsr_c, r13
410	msr	spsr, r13	@ switch modes, make sure moves will execute
411	mov	lr, pc		@ capture return pc
412	movs	pc, lr		@ jump to next instruction & switch modes.
413	.endm
414
415	.macro get_irq_stack			@ setup IRQ stack
416	ldr	sp, IRQ_STACK_START
417	.endm
418
419	.macro get_fiq_stack			@ setup FIQ stack
420	ldr	sp, FIQ_STACK_START
421	.endm
422#endif	/* CONFIG_SPL_BUILD */
423
424/*
425 * exception handlers
426 */
427#ifdef CONFIG_SPL_BUILD
428	.align	5
429do_hang:
430	ldr	sp, _TEXT_BASE			/* switch to abort stack */
4311:
432	bl	1b				/* hang and never return */
433#else	/* !CONFIG_SPL_BUILD */
434	.align  5
435undefined_instruction:
436	get_bad_stack
437	bad_save_user_regs
438	bl	do_undefined_instruction
439
440	.align	5
441software_interrupt:
442	get_bad_stack
443	bad_save_user_regs
444	bl	do_software_interrupt
445
446	.align	5
447prefetch_abort:
448	get_bad_stack
449	bad_save_user_regs
450	bl	do_prefetch_abort
451
452	.align	5
453data_abort:
454	get_bad_stack
455	bad_save_user_regs
456	bl	do_data_abort
457
458	.align	5
459not_used:
460	get_bad_stack
461	bad_save_user_regs
462	bl	do_not_used
463
464#ifdef CONFIG_USE_IRQ
465
466	.align	5
467irq:
468	get_irq_stack
469	irq_save_user_regs
470	bl	do_irq
471	irq_restore_user_regs
472
473	.align	5
474fiq:
475	get_fiq_stack
476	/* someone ought to write a more effiction fiq_save_user_regs */
477	irq_save_user_regs
478	bl	do_fiq
479	irq_restore_user_regs
480
481#else
482
483	.align	5
484irq:
485	get_bad_stack
486	bad_save_user_regs
487	bl	do_irq
488
489	.align	5
490fiq:
491	get_bad_stack
492	bad_save_user_regs
493	bl	do_fiq
494
495#endif
496#endif	/* CONFIG_SPL_BUILD */
497