1/* 2 * armboot - Startup Code for ARM926EJS CPU-core 3 * 4 * Copyright (c) 2003 Texas Instruments 5 * 6 * ----- Adapted for OMAP1610 OMAP730 from ARM925t code ------ 7 * 8 * Copyright (c) 2001 Marius Gröger <mag@sysgo.de> 9 * Copyright (c) 2002 Alex Züpke <azu@sysgo.de> 10 * Copyright (c) 2002 Gary Jennejohn <garyj@denx.de> 11 * Copyright (c) 2003 Richard Woodruff <r-woodruff2@ti.com> 12 * Copyright (c) 2003 Kshitij <kshitij@ti.com> 13 * Copyright (c) 2010 Albert Aribaud <albert.u.boot@aribaud.net> 14 * 15 * SPDX-License-Identifier: GPL-2.0+ 16 */ 17 18#include <asm-offsets.h> 19#include <config.h> 20#include <common.h> 21 22/* 23 ************************************************************************* 24 * 25 * Startup Code (reset vector) 26 * 27 * do important init only if we don't start from memory! 28 * setup Memory and board specific bits prior to relocation. 29 * relocate armboot to ram 30 * setup stack 31 * 32 ************************************************************************* 33 */ 34 35 .globl reset 36 37reset: 38 /* 39 * set the cpu to SVC32 mode 40 */ 41 mrs r0,cpsr 42 bic r0,r0,#0x1f 43 orr r0,r0,#0xd3 44 msr cpsr,r0 45 46 /* 47 * we do sys-critical inits only at reboot, 48 * not when booting from ram! 49 */ 50#ifndef CONFIG_SKIP_LOWLEVEL_INIT 51 bl cpu_init_crit 52#endif 53 54 bl _main 55 56/*------------------------------------------------------------------------------*/ 57 58 .globl c_runtime_cpu_setup 59c_runtime_cpu_setup: 60 61 bx lr 62 63/* 64 ************************************************************************* 65 * 66 * CPU_init_critical registers 67 * 68 * setup important registers 69 * setup memory timing 70 * 71 ************************************************************************* 72 */ 73#ifndef CONFIG_SKIP_LOWLEVEL_INIT 74cpu_init_crit: 75 /* 76 * flush D cache before disabling it 77 */ 78 mov r0, #0 79flush_dcache: 80 mrc p15, 0, r15, c7, c10, 3 81 bne flush_dcache 82 83 mcr p15, 0, r0, c8, c7, 0 /* invalidate TLB */ 84 mcr p15, 0, r0, c7, c5, 0 /* invalidate I Cache */ 85 86 /* 87 * disable MMU and D cache 88 * enable I cache if CONFIG_SYS_ICACHE_OFF is not defined 89 */ 90 mrc p15, 0, r0, c1, c0, 0 91 bic r0, r0, #0x00000300 /* clear bits 9:8 (---- --RS) */ 92 bic r0, r0, #0x00000087 /* clear bits 7, 2:0 (B--- -CAM) */ 93#ifdef CONFIG_SYS_EXCEPTION_VECTORS_HIGH 94 orr r0, r0, #0x00002000 /* set bit 13 (--V- ----) */ 95#else 96 bic r0, r0, #0x00002000 /* clear bit 13 (--V- ----) */ 97#endif 98 orr r0, r0, #0x00000002 /* set bit 1 (A) Align */ 99#ifndef CONFIG_SYS_ICACHE_OFF 100 orr r0, r0, #0x00001000 /* set bit 12 (I) I-Cache */ 101#endif 102 mcr p15, 0, r0, c1, c0, 0 103 104 /* 105 * Go setup Memory and board specific bits prior to relocation. 106 */ 107 mov ip, lr /* perserve link reg across call */ 108 bl lowlevel_init /* go setup pll,mux,memory */ 109 mov lr, ip /* restore link */ 110 mov pc, lr /* back to my caller */ 111#endif /* CONFIG_SKIP_LOWLEVEL_INIT */ 112