xref: /openbmc/u-boot/arch/arm/cpu/arm926ejs/start.S (revision 7c2eabab) 
1/*
2 *  armboot - Startup Code for ARM926EJS CPU-core
3 *
4 *  Copyright (c) 2003  Texas Instruments
5 *
6 *  ----- Adapted for OMAP1610 OMAP730 from ARM925t code ------
7 *
8 *  Copyright (c) 2001	Marius Gröger <mag@sysgo.de>
9 *  Copyright (c) 2002	Alex Züpke <azu@sysgo.de>
10 *  Copyright (c) 2002	Gary Jennejohn <garyj@denx.de>
11 *  Copyright (c) 2003	Richard Woodruff <r-woodruff2@ti.com>
12 *  Copyright (c) 2003	Kshitij <kshitij@ti.com>
13 *  Copyright (c) 2010	Albert Aribaud <albert.u.boot@aribaud.net>
14 *
15 * See file CREDITS for list of people who contributed to this
16 * project.
17 *
18 * This program is free software; you can redistribute it and/or
19 * modify it under the terms of the GNU General Public License as
20 * published by the Free Software Foundation; either version 2 of
21 * the License, or (at your option) any later version.
22 *
23 * This program is distributed in the hope that it will be useful,
24 * but WITHOUT ANY WARRANTY; without even the implied warranty of
25 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
26 * GNU General Public License for more details.
27 *
28 * You should have received a copy of the GNU General Public License
29 * along with this program; if not, write to the Free Software
30 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
31 * MA 02111-1307 USA
32 */
33
34#include <asm-offsets.h>
35#include <config.h>
36#include <common.h>
37#include <version.h>
38
39#if defined(CONFIG_OMAP1610)
40#include <./configs/omap1510.h>
41#elif defined(CONFIG_OMAP730)
42#include <./configs/omap730.h>
43#endif
44
45/*
46 *************************************************************************
47 *
48 * Jump vector table as in table 3.1 in [1]
49 *
50 *************************************************************************
51 */
52
53
54#ifdef CONFIG_SYS_DV_NOR_BOOT_CFG
55.globl _start
56_start:
57.globl _NOR_BOOT_CFG
58_NOR_BOOT_CFG:
59	.word	CONFIG_SYS_DV_NOR_BOOT_CFG
60	b	reset
61#else
62.globl _start
63_start:
64	b	reset
65#endif
66#ifdef CONFIG_SPL_BUILD
67/* No exception handlers in preloader */
68	ldr	pc, _hang
69	ldr	pc, _hang
70	ldr	pc, _hang
71	ldr	pc, _hang
72	ldr	pc, _hang
73	ldr	pc, _hang
74	ldr	pc, _hang
75
76_hang:
77	.word	do_hang
78/* pad to 64 byte boundary */
79	.word	0x12345678
80	.word	0x12345678
81	.word	0x12345678
82	.word	0x12345678
83	.word	0x12345678
84	.word	0x12345678
85	.word	0x12345678
86#else
87	ldr	pc, _undefined_instruction
88	ldr	pc, _software_interrupt
89	ldr	pc, _prefetch_abort
90	ldr	pc, _data_abort
91	ldr	pc, _not_used
92	ldr	pc, _irq
93	ldr	pc, _fiq
94
95_undefined_instruction:
96	.word undefined_instruction
97_software_interrupt:
98	.word software_interrupt
99_prefetch_abort:
100	.word prefetch_abort
101_data_abort:
102	.word data_abort
103_not_used:
104	.word not_used
105_irq:
106	.word irq
107_fiq:
108	.word fiq
109
110#endif	/* CONFIG_SPL_BUILD */
111	.balignl 16,0xdeadbeef
112
113
114/*
115 *************************************************************************
116 *
117 * Startup Code (reset vector)
118 *
119 * do important init only if we don't start from memory!
120 * setup Memory and board specific bits prior to relocation.
121 * relocate armboot to ram
122 * setup stack
123 *
124 *************************************************************************
125 */
126
127.globl _TEXT_BASE
128_TEXT_BASE:
129	.word	CONFIG_SYS_TEXT_BASE
130
131/*
132 * These are defined in the board-specific linker script.
133 * Subtracting _start from them lets the linker put their
134 * relative position in the executable instead of leaving
135 * them null.
136 */
137.globl _bss_start_ofs
138_bss_start_ofs:
139	.word __bss_start - _start
140
141.globl _bss_end_ofs
142_bss_end_ofs:
143	.word __bss_end__ - _start
144
145.globl _end_ofs
146_end_ofs:
147	.word _end - _start
148
149#ifdef CONFIG_USE_IRQ
150/* IRQ stack memory (calculated at run-time) */
151.globl IRQ_STACK_START
152IRQ_STACK_START:
153	.word	0x0badc0de
154
155/* IRQ stack memory (calculated at run-time) */
156.globl FIQ_STACK_START
157FIQ_STACK_START:
158	.word 0x0badc0de
159#endif
160
161/* IRQ stack memory (calculated at run-time) + 8 bytes */
162.globl IRQ_STACK_START_IN
163IRQ_STACK_START_IN:
164	.word	0x0badc0de
165
166/*
167 * the actual reset code
168 */
169
170reset:
171	/*
172	 * set the cpu to SVC32 mode
173	 */
174	mrs	r0,cpsr
175	bic	r0,r0,#0x1f
176	orr	r0,r0,#0xd3
177	msr	cpsr,r0
178
179	/*
180	 * we do sys-critical inits only at reboot,
181	 * not when booting from ram!
182	 */
183#ifndef CONFIG_SKIP_LOWLEVEL_INIT
184	bl	cpu_init_crit
185#endif
186
187/* Set stackpointer in internal RAM to call board_init_f */
188call_board_init_f:
189	ldr	sp, =(CONFIG_SYS_INIT_SP_ADDR)
190	bic	sp, sp, #7 /* 8-byte alignment for ABI compliance */
191	ldr	r0,=0x00000000
192	bl	board_init_f
193
194/*------------------------------------------------------------------------------*/
195
196/*
197 * void relocate_code (addr_sp, gd, addr_moni)
198 *
199 * This "function" does not return, instead it continues in RAM
200 * after relocating the monitor code.
201 *
202 */
203	.globl	relocate_code
204relocate_code:
205	mov	r4, r0	/* save addr_sp */
206	mov	r5, r1	/* save addr of gd */
207	mov	r6, r2	/* save addr of destination */
208
209	/* Set up the stack						    */
210stack_setup:
211	mov	sp, r4
212
213	adr	r0, _start
214	cmp	r0, r6
215	beq	clear_bss		/* skip relocation */
216	mov	r1, r6			/* r1 <- scratch for copy loop */
217	ldr	r3, _bss_start_ofs
218	add	r2, r0, r3		/* r2 <- source end address	    */
219
220copy_loop:
221	ldmia	r0!, {r9-r10}		/* copy from source address [r0]    */
222	stmia	r1!, {r9-r10}		/* copy to   target address [r1]    */
223	cmp	r0, r2			/* until source end address [r2]    */
224	blo	copy_loop
225
226#ifndef CONFIG_SPL_BUILD
227	/*
228	 * fix .rel.dyn relocations
229	 */
230	ldr	r0, _TEXT_BASE		/* r0 <- Text base */
231	sub	r9, r6, r0		/* r9 <- relocation offset */
232	ldr	r10, _dynsym_start_ofs	/* r10 <- sym table ofs */
233	add	r10, r10, r0		/* r10 <- sym table in FLASH */
234	ldr	r2, _rel_dyn_start_ofs	/* r2 <- rel dyn start ofs */
235	add	r2, r2, r0		/* r2 <- rel dyn start in FLASH */
236	ldr	r3, _rel_dyn_end_ofs	/* r3 <- rel dyn end ofs */
237	add	r3, r3, r0		/* r3 <- rel dyn end in FLASH */
238fixloop:
239	ldr	r0, [r2]		/* r0 <- location to fix up, IN FLASH! */
240	add	r0, r0, r9		/* r0 <- location to fix up in RAM */
241	ldr	r1, [r2, #4]
242	and	r7, r1, #0xff
243	cmp	r7, #23			/* relative fixup? */
244	beq	fixrel
245	cmp	r7, #2			/* absolute fixup? */
246	beq	fixabs
247	/* ignore unknown type of fixup */
248	b	fixnext
249fixabs:
250	/* absolute fix: set location to (offset) symbol value */
251	mov	r1, r1, LSR #4		/* r1 <- symbol index in .dynsym */
252	add	r1, r10, r1		/* r1 <- address of symbol in table */
253	ldr	r1, [r1, #4]		/* r1 <- symbol value */
254	add	r1, r1, r9		/* r1 <- relocated sym addr */
255	b	fixnext
256fixrel:
257	/* relative fix: increase location by offset */
258	ldr	r1, [r0]
259	add	r1, r1, r9
260fixnext:
261	str	r1, [r0]
262	add	r2, r2, #8		/* each rel.dyn entry is 8 bytes */
263	cmp	r2, r3
264	blo	fixloop
265#endif
266
267clear_bss:
268#ifndef CONFIG_SPL_BUILD
269	ldr	r0, _bss_start_ofs
270	ldr	r1, _bss_end_ofs
271	mov	r4, r6			/* reloc addr */
272	add	r0, r0, r4
273	add	r1, r1, r4
274	mov	r2, #0x00000000		/* clear			    */
275
276clbss_l:str	r2, [r0]		/* clear loop...		    */
277	add	r0, r0, #4
278	cmp	r0, r1
279	bne	clbss_l
280
281	bl coloured_LED_init
282	bl red_led_on
283#endif
284
285/*
286 * We are done. Do not return, instead branch to second part of board
287 * initialization, now running from RAM.
288 */
289#ifdef CONFIG_NAND_SPL
290	ldr     r0, _nand_boot_ofs
291	mov	pc, r0
292
293_nand_boot_ofs:
294	.word nand_boot
295#else
296	ldr	r0, _board_init_r_ofs
297	ldr	r1, _TEXT_BASE
298	add	lr, r0, r1
299	add	lr, lr, r9
300	/* setup parameters for board_init_r */
301	mov	r0, r5		/* gd_t */
302	mov	r1, r6		/* dest_addr */
303	/* jump to it ... */
304	mov	pc, lr
305
306_board_init_r_ofs:
307	.word board_init_r - _start
308#endif
309
310_rel_dyn_start_ofs:
311	.word __rel_dyn_start - _start
312_rel_dyn_end_ofs:
313	.word __rel_dyn_end - _start
314_dynsym_start_ofs:
315	.word __dynsym_start - _start
316
317/*
318 *************************************************************************
319 *
320 * CPU_init_critical registers
321 *
322 * setup important registers
323 * setup memory timing
324 *
325 *************************************************************************
326 */
327#ifndef CONFIG_SKIP_LOWLEVEL_INIT
328cpu_init_crit:
329	/*
330	 * flush v4 I/D caches
331	 */
332	mov	r0, #0
333	mcr	p15, 0, r0, c7, c7, 0	/* flush v3/v4 cache */
334	mcr	p15, 0, r0, c8, c7, 0	/* flush v4 TLB */
335
336	/*
337	 * disable MMU stuff and caches
338	 */
339	mrc	p15, 0, r0, c1, c0, 0
340	bic	r0, r0, #0x00002300	/* clear bits 13, 9:8 (--V- --RS) */
341	bic	r0, r0, #0x00000087	/* clear bits 7, 2:0 (B--- -CAM) */
342	orr	r0, r0, #0x00000002	/* set bit 2 (A) Align */
343	orr	r0, r0, #0x00001000	/* set bit 12 (I) I-Cache */
344	mcr	p15, 0, r0, c1, c0, 0
345
346	/*
347	 * Go setup Memory and board specific bits prior to relocation.
348	 */
349	mov	ip, lr		/* perserve link reg across call */
350	bl	lowlevel_init	/* go setup pll,mux,memory */
351	mov	lr, ip		/* restore link */
352	mov	pc, lr		/* back to my caller */
353#endif /* CONFIG_SKIP_LOWLEVEL_INIT */
354
355#ifndef CONFIG_SPL_BUILD
356/*
357 *************************************************************************
358 *
359 * Interrupt handling
360 *
361 *************************************************************************
362 */
363
364@
365@ IRQ stack frame.
366@
367#define S_FRAME_SIZE	72
368
369#define S_OLD_R0	68
370#define S_PSR		64
371#define S_PC		60
372#define S_LR		56
373#define S_SP		52
374
375#define S_IP		48
376#define S_FP		44
377#define S_R10		40
378#define S_R9		36
379#define S_R8		32
380#define S_R7		28
381#define S_R6		24
382#define S_R5		20
383#define S_R4		16
384#define S_R3		12
385#define S_R2		8
386#define S_R1		4
387#define S_R0		0
388
389#define MODE_SVC 0x13
390#define I_BIT	 0x80
391
392/*
393 * use bad_save_user_regs for abort/prefetch/undef/swi ...
394 * use irq_save_user_regs / irq_restore_user_regs for IRQ/FIQ handling
395 */
396
397	.macro	bad_save_user_regs
398	@ carve out a frame on current user stack
399	sub	sp, sp, #S_FRAME_SIZE
400	stmia	sp, {r0 - r12}	@ Save user registers (now in svc mode) r0-r12
401	ldr	r2, IRQ_STACK_START_IN
402	@ get values for "aborted" pc and cpsr (into parm regs)
403	ldmia	r2, {r2 - r3}
404	add	r0, sp, #S_FRAME_SIZE		@ grab pointer to old stack
405	add	r5, sp, #S_SP
406	mov	r1, lr
407	stmia	r5, {r0 - r3}	@ save sp_SVC, lr_SVC, pc, cpsr
408	mov	r0, sp		@ save current stack into r0 (param register)
409	.endm
410
411	.macro	irq_save_user_regs
412	sub	sp, sp, #S_FRAME_SIZE
413	stmia	sp, {r0 - r12}			@ Calling r0-r12
414	@ !!!! R8 NEEDS to be saved !!!! a reserved stack spot would be good.
415	add	r8, sp, #S_PC
416	stmdb	r8, {sp, lr}^		@ Calling SP, LR
417	str	lr, [r8, #0]		@ Save calling PC
418	mrs	r6, spsr
419	str	r6, [r8, #4]		@ Save CPSR
420	str	r0, [r8, #8]		@ Save OLD_R0
421	mov	r0, sp
422	.endm
423
424	.macro	irq_restore_user_regs
425	ldmia	sp, {r0 - lr}^			@ Calling r0 - lr
426	mov	r0, r0
427	ldr	lr, [sp, #S_PC]			@ Get PC
428	add	sp, sp, #S_FRAME_SIZE
429	subs	pc, lr, #4		@ return & move spsr_svc into cpsr
430	.endm
431
432	.macro get_bad_stack
433	ldr	r13, IRQ_STACK_START_IN		@ setup our mode stack
434
435	str	lr, [r13]	@ save caller lr in position 0 of saved stack
436	mrs	lr, spsr	@ get the spsr
437	str	lr, [r13, #4]	@ save spsr in position 1 of saved stack
438	mov	r13, #MODE_SVC	@ prepare SVC-Mode
439	@ msr	spsr_c, r13
440	msr	spsr, r13	@ switch modes, make sure moves will execute
441	mov	lr, pc		@ capture return pc
442	movs	pc, lr		@ jump to next instruction & switch modes.
443	.endm
444
445	.macro get_irq_stack			@ setup IRQ stack
446	ldr	sp, IRQ_STACK_START
447	.endm
448
449	.macro get_fiq_stack			@ setup FIQ stack
450	ldr	sp, FIQ_STACK_START
451	.endm
452#endif	/* CONFIG_SPL_BUILD */
453
454/*
455 * exception handlers
456 */
457#ifdef CONFIG_SPL_BUILD
458	.align	5
459do_hang:
460	ldr	sp, _TEXT_BASE			/* switch to abort stack */
4611:
462	bl	1b				/* hang and never return */
463#else	/* !CONFIG_SPL_BUILD */
464	.align  5
465undefined_instruction:
466	get_bad_stack
467	bad_save_user_regs
468	bl	do_undefined_instruction
469
470	.align	5
471software_interrupt:
472	get_bad_stack
473	bad_save_user_regs
474	bl	do_software_interrupt
475
476	.align	5
477prefetch_abort:
478	get_bad_stack
479	bad_save_user_regs
480	bl	do_prefetch_abort
481
482	.align	5
483data_abort:
484	get_bad_stack
485	bad_save_user_regs
486	bl	do_data_abort
487
488	.align	5
489not_used:
490	get_bad_stack
491	bad_save_user_regs
492	bl	do_not_used
493
494#ifdef CONFIG_USE_IRQ
495
496	.align	5
497irq:
498	get_irq_stack
499	irq_save_user_regs
500	bl	do_irq
501	irq_restore_user_regs
502
503	.align	5
504fiq:
505	get_fiq_stack
506	/* someone ought to write a more effiction fiq_save_user_regs */
507	irq_save_user_regs
508	bl	do_fiq
509	irq_restore_user_regs
510
511#else
512
513	.align	5
514irq:
515	get_bad_stack
516	bad_save_user_regs
517	bl	do_irq
518
519	.align	5
520fiq:
521	get_bad_stack
522	bad_save_user_regs
523	bl	do_fiq
524
525#endif
526#endif	/* CONFIG_SPL_BUILD */
527