184ad6884SPeter Tyser/* 284ad6884SPeter Tyser * armboot - Startup Code for ARM926EJS CPU-core 384ad6884SPeter Tyser * 484ad6884SPeter Tyser * Copyright (c) 2003 Texas Instruments 584ad6884SPeter Tyser * 684ad6884SPeter Tyser * ----- Adapted for OMAP1610 OMAP730 from ARM925t code ------ 784ad6884SPeter Tyser * 8fa82f871SAlbert ARIBAUD * Copyright (c) 2001 Marius Gröger <mag@sysgo.de> 9fa82f871SAlbert ARIBAUD * Copyright (c) 2002 Alex Züpke <azu@sysgo.de> 1084ad6884SPeter Tyser * Copyright (c) 2002 Gary Jennejohn <garyj@denx.de> 1184ad6884SPeter Tyser * Copyright (c) 2003 Richard Woodruff <r-woodruff2@ti.com> 1284ad6884SPeter Tyser * Copyright (c) 2003 Kshitij <kshitij@ti.com> 1357b4bce9SAlbert ARIBAUD * Copyright (c) 2010 Albert Aribaud <albert.u.boot@aribaud.net> 1484ad6884SPeter Tyser * 1584ad6884SPeter Tyser * See file CREDITS for list of people who contributed to this 1684ad6884SPeter Tyser * project. 1784ad6884SPeter Tyser * 1884ad6884SPeter Tyser * This program is free software; you can redistribute it and/or 1984ad6884SPeter Tyser * modify it under the terms of the GNU General Public License as 2084ad6884SPeter Tyser * published by the Free Software Foundation; either version 2 of 2184ad6884SPeter Tyser * the License, or (at your option) any later version. 2284ad6884SPeter Tyser * 2384ad6884SPeter Tyser * This program is distributed in the hope that it will be useful, 2484ad6884SPeter Tyser * but WITHOUT ANY WARRANTY; without even the implied warranty of 2584ad6884SPeter Tyser * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 2684ad6884SPeter Tyser * GNU General Public License for more details. 2784ad6884SPeter Tyser * 2884ad6884SPeter Tyser * You should have received a copy of the GNU General Public License 2984ad6884SPeter Tyser * along with this program; if not, write to the Free Software 3084ad6884SPeter Tyser * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 3184ad6884SPeter Tyser * MA 02111-1307 USA 3284ad6884SPeter Tyser */ 3384ad6884SPeter Tyser 3425ddd1fbSWolfgang Denk#include <asm-offsets.h> 3584ad6884SPeter Tyser#include <config.h> 3684ad6884SPeter Tyser#include <common.h> 3784ad6884SPeter Tyser#include <version.h> 3884ad6884SPeter Tyser 3984ad6884SPeter Tyser#if defined(CONFIG_OMAP1610) 4084ad6884SPeter Tyser#include <./configs/omap1510.h> 4184ad6884SPeter Tyser#elif defined(CONFIG_OMAP730) 4284ad6884SPeter Tyser#include <./configs/omap730.h> 4384ad6884SPeter Tyser#endif 4484ad6884SPeter Tyser 4584ad6884SPeter Tyser/* 4684ad6884SPeter Tyser ************************************************************************* 4784ad6884SPeter Tyser * 4884ad6884SPeter Tyser * Jump vector table as in table 3.1 in [1] 4984ad6884SPeter Tyser * 5084ad6884SPeter Tyser ************************************************************************* 5184ad6884SPeter Tyser */ 5284ad6884SPeter Tyser 5384ad6884SPeter Tyser 54337c4333SHeiko Schocher#ifdef CONFIG_SYS_DV_NOR_BOOT_CFG 55337c4333SHeiko Schocher.globl _start 56337c4333SHeiko Schocher_start: 57337c4333SHeiko Schocher.globl _NOR_BOOT_CFG 58337c4333SHeiko Schocher_NOR_BOOT_CFG: 59337c4333SHeiko Schocher .word CONFIG_SYS_DV_NOR_BOOT_CFG 60337c4333SHeiko Schocher b reset 61337c4333SHeiko Schocher#else 6284ad6884SPeter Tyser.globl _start 6384ad6884SPeter Tyser_start: 6484ad6884SPeter Tyser b reset 65337c4333SHeiko Schocher#endif 66401bb30bSAneesh V#ifdef CONFIG_SPL_BUILD 6784ad6884SPeter Tyser/* No exception handlers in preloader */ 6884ad6884SPeter Tyser ldr pc, _hang 6984ad6884SPeter Tyser ldr pc, _hang 7084ad6884SPeter Tyser ldr pc, _hang 7184ad6884SPeter Tyser ldr pc, _hang 7284ad6884SPeter Tyser ldr pc, _hang 7384ad6884SPeter Tyser ldr pc, _hang 7484ad6884SPeter Tyser ldr pc, _hang 7584ad6884SPeter Tyser 7684ad6884SPeter Tyser_hang: 7784ad6884SPeter Tyser .word do_hang 7884ad6884SPeter Tyser/* pad to 64 byte boundary */ 7984ad6884SPeter Tyser .word 0x12345678 8084ad6884SPeter Tyser .word 0x12345678 8184ad6884SPeter Tyser .word 0x12345678 8284ad6884SPeter Tyser .word 0x12345678 8384ad6884SPeter Tyser .word 0x12345678 8484ad6884SPeter Tyser .word 0x12345678 8584ad6884SPeter Tyser .word 0x12345678 8684ad6884SPeter Tyser#else 8784ad6884SPeter Tyser ldr pc, _undefined_instruction 8884ad6884SPeter Tyser ldr pc, _software_interrupt 8984ad6884SPeter Tyser ldr pc, _prefetch_abort 9084ad6884SPeter Tyser ldr pc, _data_abort 9184ad6884SPeter Tyser ldr pc, _not_used 9284ad6884SPeter Tyser ldr pc, _irq 9384ad6884SPeter Tyser ldr pc, _fiq 9484ad6884SPeter Tyser 9584ad6884SPeter Tyser_undefined_instruction: 9684ad6884SPeter Tyser .word undefined_instruction 9784ad6884SPeter Tyser_software_interrupt: 9884ad6884SPeter Tyser .word software_interrupt 9984ad6884SPeter Tyser_prefetch_abort: 10084ad6884SPeter Tyser .word prefetch_abort 10184ad6884SPeter Tyser_data_abort: 10284ad6884SPeter Tyser .word data_abort 10384ad6884SPeter Tyser_not_used: 10484ad6884SPeter Tyser .word not_used 10584ad6884SPeter Tyser_irq: 10684ad6884SPeter Tyser .word irq 10784ad6884SPeter Tyser_fiq: 10884ad6884SPeter Tyser .word fiq 10984ad6884SPeter Tyser 110401bb30bSAneesh V#endif /* CONFIG_SPL_BUILD */ 11184ad6884SPeter Tyser .balignl 16,0xdeadbeef 11284ad6884SPeter Tyser 11384ad6884SPeter Tyser 11484ad6884SPeter Tyser/* 11584ad6884SPeter Tyser ************************************************************************* 11684ad6884SPeter Tyser * 11784ad6884SPeter Tyser * Startup Code (reset vector) 11884ad6884SPeter Tyser * 11984ad6884SPeter Tyser * do important init only if we don't start from memory! 12084ad6884SPeter Tyser * setup Memory and board specific bits prior to relocation. 12184ad6884SPeter Tyser * relocate armboot to ram 12284ad6884SPeter Tyser * setup stack 12384ad6884SPeter Tyser * 12484ad6884SPeter Tyser ************************************************************************* 12584ad6884SPeter Tyser */ 12684ad6884SPeter Tyser 127ab86f72cSHeiko Schocher.globl _TEXT_BASE 12884ad6884SPeter Tyser_TEXT_BASE: 129435199f3SHeiko Schocher#ifdef CONFIG_NAND_SPL /* deprecated, use instead CONFIG_SPL_BUILD */ 13014d0a02aSWolfgang Denk .word CONFIG_SYS_TEXT_BASE 131435199f3SHeiko Schocher#else 132435199f3SHeiko Schocher#ifdef CONFIG_SPL_BUILD 133435199f3SHeiko Schocher .word CONFIG_SPL_TEXT_BASE 134435199f3SHeiko Schocher#else 135435199f3SHeiko Schocher .word CONFIG_SYS_TEXT_BASE 136435199f3SHeiko Schocher#endif 137435199f3SHeiko Schocher#endif 13884ad6884SPeter Tyser 13984ad6884SPeter Tyser/* 14084ad6884SPeter Tyser * These are defined in the board-specific linker script. 14192d5ecbaSAlbert Aribaud * Subtracting _start from them lets the linker put their 14292d5ecbaSAlbert Aribaud * relative position in the executable instead of leaving 14392d5ecbaSAlbert Aribaud * them null. 14484ad6884SPeter Tyser */ 14592d5ecbaSAlbert Aribaud.globl _bss_start_ofs 14692d5ecbaSAlbert Aribaud_bss_start_ofs: 14792d5ecbaSAlbert Aribaud .word __bss_start - _start 14884ad6884SPeter Tyser 14992d5ecbaSAlbert Aribaud.globl _bss_end_ofs 15092d5ecbaSAlbert Aribaud_bss_end_ofs: 15144c6e659SPo-Yu Chuang .word __bss_end__ - _start 15284ad6884SPeter Tyser 153f326cbbaSPo-Yu Chuang.globl _end_ofs 154f326cbbaSPo-Yu Chuang_end_ofs: 155f326cbbaSPo-Yu Chuang .word _end - _start 156f326cbbaSPo-Yu Chuang 1576a6e1677SHeiko Schocher#ifdef CONFIG_NAND_U_BOOT 1586a6e1677SHeiko Schocher.globl _end 1596a6e1677SHeiko Schocher_end: 1606a6e1677SHeiko Schocher .word __bss_end__ 1616a6e1677SHeiko Schocher#endif 1626a6e1677SHeiko Schocher 16384ad6884SPeter Tyser#ifdef CONFIG_USE_IRQ 16484ad6884SPeter Tyser/* IRQ stack memory (calculated at run-time) */ 16584ad6884SPeter Tyser.globl IRQ_STACK_START 16684ad6884SPeter TyserIRQ_STACK_START: 16784ad6884SPeter Tyser .word 0x0badc0de 16884ad6884SPeter Tyser 16984ad6884SPeter Tyser/* IRQ stack memory (calculated at run-time) */ 17084ad6884SPeter Tyser.globl FIQ_STACK_START 17184ad6884SPeter TyserFIQ_STACK_START: 17284ad6884SPeter Tyser .word 0x0badc0de 17384ad6884SPeter Tyser#endif 17484ad6884SPeter Tyser 175ab86f72cSHeiko Schocher/* IRQ stack memory (calculated at run-time) + 8 bytes */ 176ab86f72cSHeiko Schocher.globl IRQ_STACK_START_IN 177ab86f72cSHeiko SchocherIRQ_STACK_START_IN: 178ab86f72cSHeiko Schocher .word 0x0badc0de 17984ad6884SPeter Tyser 180ab86f72cSHeiko Schocher/* 181ab86f72cSHeiko Schocher * the actual reset code 182ab86f72cSHeiko Schocher */ 183ab86f72cSHeiko Schocher 184ab86f72cSHeiko Schocherreset: 185ab86f72cSHeiko Schocher /* 186ab86f72cSHeiko Schocher * set the cpu to SVC32 mode 187ab86f72cSHeiko Schocher */ 188ab86f72cSHeiko Schocher mrs r0,cpsr 189ab86f72cSHeiko Schocher bic r0,r0,#0x1f 190ab86f72cSHeiko Schocher orr r0,r0,#0xd3 191ab86f72cSHeiko Schocher msr cpsr,r0 192ab86f72cSHeiko Schocher 193ab86f72cSHeiko Schocher /* 194ab86f72cSHeiko Schocher * we do sys-critical inits only at reboot, 195ab86f72cSHeiko Schocher * not when booting from ram! 196ab86f72cSHeiko Schocher */ 197ab86f72cSHeiko Schocher bl cpu_init_crit 198ab86f72cSHeiko Schocher 199ab86f72cSHeiko Schocher/* Set stackpointer in internal RAM to call board_init_f */ 200ab86f72cSHeiko Schochercall_board_init_f: 201435199f3SHeiko Schocher#ifdef CONFIG_NAND_SPL /* deprecated, use instead CONFIG_SPL_BUILD */ 202ab86f72cSHeiko Schocher ldr sp, =(CONFIG_SYS_INIT_SP_ADDR) 203435199f3SHeiko Schocher#else 204435199f3SHeiko Schocher#ifdef CONFIG_SPL_BUILD 205435199f3SHeiko Schocher ldr sp, =(CONFIG_SPL_STACK) 206435199f3SHeiko Schocher#else 207435199f3SHeiko Schocher ldr sp, =(CONFIG_SYS_INIT_SP_ADDR) 208435199f3SHeiko Schocher#endif 209435199f3SHeiko Schocher#endif 210296cae73SHeiko Schocher bic sp, sp, #7 /* 8-byte alignment for ABI compliance */ 211ab86f72cSHeiko Schocher ldr r0,=0x00000000 212ab86f72cSHeiko Schocher bl board_init_f 213ab86f72cSHeiko Schocher 214ab86f72cSHeiko Schocher/*------------------------------------------------------------------------------*/ 215ab86f72cSHeiko Schocher 216ab86f72cSHeiko Schocher/* 217ab86f72cSHeiko Schocher * void relocate_code (addr_sp, gd, addr_moni) 218ab86f72cSHeiko Schocher * 219ab86f72cSHeiko Schocher * This "function" does not return, instead it continues in RAM 220ab86f72cSHeiko Schocher * after relocating the monitor code. 221ab86f72cSHeiko Schocher * 222ab86f72cSHeiko Schocher */ 223ab86f72cSHeiko Schocher .globl relocate_code 224ab86f72cSHeiko Schocherrelocate_code: 225ab86f72cSHeiko Schocher mov r4, r0 /* save addr_sp */ 226ab86f72cSHeiko Schocher mov r5, r1 /* save addr of gd */ 227ab86f72cSHeiko Schocher mov r6, r2 /* save addr of destination */ 228ab86f72cSHeiko Schocher 229ab86f72cSHeiko Schocher /* Set up the stack */ 230ab86f72cSHeiko Schocherstack_setup: 231ab86f72cSHeiko Schocher mov sp, r4 232ab86f72cSHeiko Schocher 233ab86f72cSHeiko Schocher adr r0, _start 234435199f3SHeiko Schocher sub r9, r6, r0 /* r9 <- relocation offset */ 235a1a47d3cSAndreas Bießmann cmp r0, r6 236a1a47d3cSAndreas Bießmann beq clear_bss /* skip relocation */ 237a78fb68fSAndreas Bießmann mov r1, r6 /* r1 <- scratch for copy loop */ 23892d5ecbaSAlbert Aribaud ldr r3, _bss_start_ofs 23992d5ecbaSAlbert Aribaud add r2, r0, r3 /* r2 <- source end address */ 240ab86f72cSHeiko Schocher 241ab86f72cSHeiko Schochercopy_loop: 242ab86f72cSHeiko Schocher ldmia r0!, {r9-r10} /* copy from source address [r0] */ 243a78fb68fSAndreas Bießmann stmia r1!, {r9-r10} /* copy to target address [r1] */ 244da90d4ceSAlbert Aribaud cmp r0, r2 /* until source end address [r2] */ 245da90d4ceSAlbert Aribaud blo copy_loop 246ab86f72cSHeiko Schocher 247401bb30bSAneesh V#ifndef CONFIG_SPL_BUILD 24892d5ecbaSAlbert Aribaud /* 24992d5ecbaSAlbert Aribaud * fix .rel.dyn relocations 25092d5ecbaSAlbert Aribaud */ 25192d5ecbaSAlbert Aribaud ldr r0, _TEXT_BASE /* r0 <- Text base */ 252a78fb68fSAndreas Bießmann sub r9, r6, r0 /* r9 <- relocation offset */ 25392d5ecbaSAlbert Aribaud ldr r10, _dynsym_start_ofs /* r10 <- sym table ofs */ 25492d5ecbaSAlbert Aribaud add r10, r10, r0 /* r10 <- sym table in FLASH */ 25592d5ecbaSAlbert Aribaud ldr r2, _rel_dyn_start_ofs /* r2 <- rel dyn start ofs */ 25692d5ecbaSAlbert Aribaud add r2, r2, r0 /* r2 <- rel dyn start in FLASH */ 25792d5ecbaSAlbert Aribaud ldr r3, _rel_dyn_end_ofs /* r3 <- rel dyn end ofs */ 25892d5ecbaSAlbert Aribaud add r3, r3, r0 /* r3 <- rel dyn end in FLASH */ 259ab86f72cSHeiko Schocherfixloop: 26092d5ecbaSAlbert Aribaud ldr r0, [r2] /* r0 <- location to fix up, IN FLASH! */ 2618c0c2b90SGray Remlin add r0, r0, r9 /* r0 <- location to fix up in RAM */ 26292d5ecbaSAlbert Aribaud ldr r1, [r2, #4] 2631f52d89fSAndreas Bießmann and r7, r1, #0xff 2641f52d89fSAndreas Bießmann cmp r7, #23 /* relative fixup? */ 26592d5ecbaSAlbert Aribaud beq fixrel 2661f52d89fSAndreas Bießmann cmp r7, #2 /* absolute fixup? */ 26792d5ecbaSAlbert Aribaud beq fixabs 26892d5ecbaSAlbert Aribaud /* ignore unknown type of fixup */ 26992d5ecbaSAlbert Aribaud b fixnext 27092d5ecbaSAlbert Aribaudfixabs: 27192d5ecbaSAlbert Aribaud /* absolute fix: set location to (offset) symbol value */ 27292d5ecbaSAlbert Aribaud mov r1, r1, LSR #4 /* r1 <- symbol index in .dynsym */ 27392d5ecbaSAlbert Aribaud add r1, r10, r1 /* r1 <- address of symbol in table */ 27492d5ecbaSAlbert Aribaud ldr r1, [r1, #4] /* r1 <- symbol value */ 2753600945bSWolfgang Denk add r1, r1, r9 /* r1 <- relocated sym addr */ 27692d5ecbaSAlbert Aribaud b fixnext 27792d5ecbaSAlbert Aribaudfixrel: 27892d5ecbaSAlbert Aribaud /* relative fix: increase location by offset */ 27992d5ecbaSAlbert Aribaud ldr r1, [r0] 28092d5ecbaSAlbert Aribaud add r1, r1, r9 28192d5ecbaSAlbert Aribaudfixnext: 28292d5ecbaSAlbert Aribaud str r1, [r0] 28392d5ecbaSAlbert Aribaud add r2, r2, #8 /* each rel.dyn entry is 8 bytes */ 284ab86f72cSHeiko Schocher cmp r2, r3 28592d5ecbaSAlbert Aribaud blo fixloop 286ab86f72cSHeiko Schocher#endif 287ab86f72cSHeiko Schocher 288ab86f72cSHeiko Schocherclear_bss: 289435199f3SHeiko Schocher#ifdef CONFIG_SPL_BUILD 290435199f3SHeiko Schocher /* No relocation for SPL */ 291435199f3SHeiko Schocher ldr r0, =__bss_start 292435199f3SHeiko Schocher ldr r1, =__bss_end__ 293435199f3SHeiko Schocher#else 29492d5ecbaSAlbert Aribaud ldr r0, _bss_start_ofs 29592d5ecbaSAlbert Aribaud ldr r1, _bss_end_ofs 296a78fb68fSAndreas Bießmann mov r4, r6 /* reloc addr */ 297ab86f72cSHeiko Schocher add r0, r0, r4 298ab86f72cSHeiko Schocher add r1, r1, r4 299435199f3SHeiko Schocher#endif 300ab86f72cSHeiko Schocher mov r2, #0x00000000 /* clear */ 301ab86f72cSHeiko Schocher 3028f1da535SChristian Rieschclbss_l:cmp r0, r1 /* clear loop... */ 3038f1da535SChristian Riesch bhs clbss_e /* if reached end of bss, exit */ 3048f1da535SChristian Riesch str r2, [r0] 305ab86f72cSHeiko Schocher add r0, r0, #4 3068f1da535SChristian Riesch b clbss_l 3078f1da535SChristian Rieschclbss_e: 308ab86f72cSHeiko Schocher 309435199f3SHeiko Schocher#ifndef CONFIG_SPL_BUILD 310ab86f72cSHeiko Schocher bl coloured_LED_init 3112d3be7c4SJason Kridner bl red_led_on 312ab86f72cSHeiko Schocher#endif 313ab86f72cSHeiko Schocher 314ab86f72cSHeiko Schocher/* 315ab86f72cSHeiko Schocher * We are done. Do not return, instead branch to second part of board 316ab86f72cSHeiko Schocher * initialization, now running from RAM. 317ab86f72cSHeiko Schocher */ 318ab86f72cSHeiko Schocher#ifdef CONFIG_NAND_SPL 31992d5ecbaSAlbert Aribaud ldr r0, _nand_boot_ofs 3209710504dSHeiko Schocher mov pc, r0 321ab86f72cSHeiko Schocher 3229710504dSHeiko Schocher_nand_boot_ofs: 3239710504dSHeiko Schocher .word nand_boot 324ab86f72cSHeiko Schocher#else 32592d5ecbaSAlbert Aribaud ldr r0, _board_init_r_ofs 3266087f1a9SAlexander Stein ldr r1, _TEXT_BASE 327123fb7deSDarius Augulis add lr, r0, r1 328123fb7deSDarius Augulis add lr, lr, r9 329ab86f72cSHeiko Schocher /* setup parameters for board_init_r */ 330ab86f72cSHeiko Schocher mov r0, r5 /* gd_t */ 331a78fb68fSAndreas Bießmann mov r1, r6 /* dest_addr */ 332ab86f72cSHeiko Schocher /* jump to it ... */ 333ab86f72cSHeiko Schocher mov pc, lr 334ab86f72cSHeiko Schocher 33592d5ecbaSAlbert Aribaud_board_init_r_ofs: 33692d5ecbaSAlbert Aribaud .word board_init_r - _start 337ab86f72cSHeiko Schocher#endif 338ab86f72cSHeiko Schocher 33992d5ecbaSAlbert Aribaud_rel_dyn_start_ofs: 34092d5ecbaSAlbert Aribaud .word __rel_dyn_start - _start 34192d5ecbaSAlbert Aribaud_rel_dyn_end_ofs: 34292d5ecbaSAlbert Aribaud .word __rel_dyn_end - _start 34392d5ecbaSAlbert Aribaud_dynsym_start_ofs: 34492d5ecbaSAlbert Aribaud .word __dynsym_start - _start 34592d5ecbaSAlbert Aribaud 34684ad6884SPeter Tyser/* 34784ad6884SPeter Tyser ************************************************************************* 34884ad6884SPeter Tyser * 34984ad6884SPeter Tyser * CPU_init_critical registers 35084ad6884SPeter Tyser * 35184ad6884SPeter Tyser * setup important registers 35284ad6884SPeter Tyser * setup memory timing 35384ad6884SPeter Tyser * 35484ad6884SPeter Tyser ************************************************************************* 35584ad6884SPeter Tyser */ 35684ad6884SPeter Tysercpu_init_crit: 35784ad6884SPeter Tyser /* 35884ad6884SPeter Tyser * flush v4 I/D caches 35984ad6884SPeter Tyser */ 36084ad6884SPeter Tyser mov r0, #0 36184ad6884SPeter Tyser mcr p15, 0, r0, c7, c7, 0 /* flush v3/v4 cache */ 36284ad6884SPeter Tyser mcr p15, 0, r0, c8, c7, 0 /* flush v4 TLB */ 36384ad6884SPeter Tyser 36484ad6884SPeter Tyser /* 36584ad6884SPeter Tyser * disable MMU stuff and caches 36684ad6884SPeter Tyser */ 36784ad6884SPeter Tyser mrc p15, 0, r0, c1, c0, 0 36884ad6884SPeter Tyser bic r0, r0, #0x00002300 /* clear bits 13, 9:8 (--V- --RS) */ 36984ad6884SPeter Tyser bic r0, r0, #0x00000087 /* clear bits 7, 2:0 (B--- -CAM) */ 37084ad6884SPeter Tyser orr r0, r0, #0x00000002 /* set bit 2 (A) Align */ 37184ad6884SPeter Tyser orr r0, r0, #0x00001000 /* set bit 12 (I) I-Cache */ 37284ad6884SPeter Tyser mcr p15, 0, r0, c1, c0, 0 37384ad6884SPeter Tyser 374*ca4b5580SHeiko Schocher#ifndef CONFIG_SKIP_LOWLEVEL_INIT 37584ad6884SPeter Tyser /* 37684ad6884SPeter Tyser * Go setup Memory and board specific bits prior to relocation. 37784ad6884SPeter Tyser */ 37884ad6884SPeter Tyser mov ip, lr /* perserve link reg across call */ 37984ad6884SPeter Tyser bl lowlevel_init /* go setup pll,mux,memory */ 38084ad6884SPeter Tyser mov lr, ip /* restore link */ 38184ad6884SPeter Tyser#endif /* CONFIG_SKIP_LOWLEVEL_INIT */ 382*ca4b5580SHeiko Schocher mov pc, lr /* back to my caller */ 38384ad6884SPeter Tyser 384401bb30bSAneesh V#ifndef CONFIG_SPL_BUILD 38584ad6884SPeter Tyser/* 38684ad6884SPeter Tyser ************************************************************************* 38784ad6884SPeter Tyser * 38884ad6884SPeter Tyser * Interrupt handling 38984ad6884SPeter Tyser * 39084ad6884SPeter Tyser ************************************************************************* 39184ad6884SPeter Tyser */ 39284ad6884SPeter Tyser 39384ad6884SPeter Tyser@ 39484ad6884SPeter Tyser@ IRQ stack frame. 39584ad6884SPeter Tyser@ 39684ad6884SPeter Tyser#define S_FRAME_SIZE 72 39784ad6884SPeter Tyser 39884ad6884SPeter Tyser#define S_OLD_R0 68 39984ad6884SPeter Tyser#define S_PSR 64 40084ad6884SPeter Tyser#define S_PC 60 40184ad6884SPeter Tyser#define S_LR 56 40284ad6884SPeter Tyser#define S_SP 52 40384ad6884SPeter Tyser 40484ad6884SPeter Tyser#define S_IP 48 40584ad6884SPeter Tyser#define S_FP 44 40684ad6884SPeter Tyser#define S_R10 40 40784ad6884SPeter Tyser#define S_R9 36 40884ad6884SPeter Tyser#define S_R8 32 40984ad6884SPeter Tyser#define S_R7 28 41084ad6884SPeter Tyser#define S_R6 24 41184ad6884SPeter Tyser#define S_R5 20 41284ad6884SPeter Tyser#define S_R4 16 41384ad6884SPeter Tyser#define S_R3 12 41484ad6884SPeter Tyser#define S_R2 8 41584ad6884SPeter Tyser#define S_R1 4 41684ad6884SPeter Tyser#define S_R0 0 41784ad6884SPeter Tyser 41884ad6884SPeter Tyser#define MODE_SVC 0x13 41984ad6884SPeter Tyser#define I_BIT 0x80 42084ad6884SPeter Tyser 42184ad6884SPeter Tyser/* 42284ad6884SPeter Tyser * use bad_save_user_regs for abort/prefetch/undef/swi ... 42384ad6884SPeter Tyser * use irq_save_user_regs / irq_restore_user_regs for IRQ/FIQ handling 42484ad6884SPeter Tyser */ 42584ad6884SPeter Tyser 42684ad6884SPeter Tyser .macro bad_save_user_regs 42784ad6884SPeter Tyser @ carve out a frame on current user stack 42884ad6884SPeter Tyser sub sp, sp, #S_FRAME_SIZE 42984ad6884SPeter Tyser stmia sp, {r0 - r12} @ Save user registers (now in svc mode) r0-r12 430ab86f72cSHeiko Schocher ldr r2, IRQ_STACK_START_IN 43184ad6884SPeter Tyser @ get values for "aborted" pc and cpsr (into parm regs) 43284ad6884SPeter Tyser ldmia r2, {r2 - r3} 43384ad6884SPeter Tyser add r0, sp, #S_FRAME_SIZE @ grab pointer to old stack 43484ad6884SPeter Tyser add r5, sp, #S_SP 43584ad6884SPeter Tyser mov r1, lr 43684ad6884SPeter Tyser stmia r5, {r0 - r3} @ save sp_SVC, lr_SVC, pc, cpsr 43784ad6884SPeter Tyser mov r0, sp @ save current stack into r0 (param register) 43884ad6884SPeter Tyser .endm 43984ad6884SPeter Tyser 44084ad6884SPeter Tyser .macro irq_save_user_regs 44184ad6884SPeter Tyser sub sp, sp, #S_FRAME_SIZE 44284ad6884SPeter Tyser stmia sp, {r0 - r12} @ Calling r0-r12 44384ad6884SPeter Tyser @ !!!! R8 NEEDS to be saved !!!! a reserved stack spot would be good. 44484ad6884SPeter Tyser add r8, sp, #S_PC 44584ad6884SPeter Tyser stmdb r8, {sp, lr}^ @ Calling SP, LR 44684ad6884SPeter Tyser str lr, [r8, #0] @ Save calling PC 44784ad6884SPeter Tyser mrs r6, spsr 44884ad6884SPeter Tyser str r6, [r8, #4] @ Save CPSR 44984ad6884SPeter Tyser str r0, [r8, #8] @ Save OLD_R0 45084ad6884SPeter Tyser mov r0, sp 45184ad6884SPeter Tyser .endm 45284ad6884SPeter Tyser 45384ad6884SPeter Tyser .macro irq_restore_user_regs 45484ad6884SPeter Tyser ldmia sp, {r0 - lr}^ @ Calling r0 - lr 45584ad6884SPeter Tyser mov r0, r0 45684ad6884SPeter Tyser ldr lr, [sp, #S_PC] @ Get PC 45784ad6884SPeter Tyser add sp, sp, #S_FRAME_SIZE 45884ad6884SPeter Tyser subs pc, lr, #4 @ return & move spsr_svc into cpsr 45984ad6884SPeter Tyser .endm 46084ad6884SPeter Tyser 46184ad6884SPeter Tyser .macro get_bad_stack 462ab86f72cSHeiko Schocher ldr r13, IRQ_STACK_START_IN @ setup our mode stack 46384ad6884SPeter Tyser 46484ad6884SPeter Tyser str lr, [r13] @ save caller lr in position 0 of saved stack 46584ad6884SPeter Tyser mrs lr, spsr @ get the spsr 46684ad6884SPeter Tyser str lr, [r13, #4] @ save spsr in position 1 of saved stack 46784ad6884SPeter Tyser mov r13, #MODE_SVC @ prepare SVC-Mode 46884ad6884SPeter Tyser @ msr spsr_c, r13 46984ad6884SPeter Tyser msr spsr, r13 @ switch modes, make sure moves will execute 47084ad6884SPeter Tyser mov lr, pc @ capture return pc 47184ad6884SPeter Tyser movs pc, lr @ jump to next instruction & switch modes. 47284ad6884SPeter Tyser .endm 47384ad6884SPeter Tyser 47484ad6884SPeter Tyser .macro get_irq_stack @ setup IRQ stack 47584ad6884SPeter Tyser ldr sp, IRQ_STACK_START 47684ad6884SPeter Tyser .endm 47784ad6884SPeter Tyser 47884ad6884SPeter Tyser .macro get_fiq_stack @ setup FIQ stack 47984ad6884SPeter Tyser ldr sp, FIQ_STACK_START 48084ad6884SPeter Tyser .endm 481401bb30bSAneesh V#endif /* CONFIG_SPL_BUILD */ 48284ad6884SPeter Tyser 48384ad6884SPeter Tyser/* 48484ad6884SPeter Tyser * exception handlers 48584ad6884SPeter Tyser */ 486401bb30bSAneesh V#ifdef CONFIG_SPL_BUILD 48784ad6884SPeter Tyser .align 5 48884ad6884SPeter Tyserdo_hang: 48984ad6884SPeter Tyser ldr sp, _TEXT_BASE /* switch to abort stack */ 49084ad6884SPeter Tyser1: 49184ad6884SPeter Tyser bl 1b /* hang and never return */ 492401bb30bSAneesh V#else /* !CONFIG_SPL_BUILD */ 49384ad6884SPeter Tyser .align 5 49484ad6884SPeter Tyserundefined_instruction: 49584ad6884SPeter Tyser get_bad_stack 49684ad6884SPeter Tyser bad_save_user_regs 49784ad6884SPeter Tyser bl do_undefined_instruction 49884ad6884SPeter Tyser 49984ad6884SPeter Tyser .align 5 50084ad6884SPeter Tysersoftware_interrupt: 50184ad6884SPeter Tyser get_bad_stack 50284ad6884SPeter Tyser bad_save_user_regs 50384ad6884SPeter Tyser bl do_software_interrupt 50484ad6884SPeter Tyser 50584ad6884SPeter Tyser .align 5 50684ad6884SPeter Tyserprefetch_abort: 50784ad6884SPeter Tyser get_bad_stack 50884ad6884SPeter Tyser bad_save_user_regs 50984ad6884SPeter Tyser bl do_prefetch_abort 51084ad6884SPeter Tyser 51184ad6884SPeter Tyser .align 5 51284ad6884SPeter Tyserdata_abort: 51384ad6884SPeter Tyser get_bad_stack 51484ad6884SPeter Tyser bad_save_user_regs 51584ad6884SPeter Tyser bl do_data_abort 51684ad6884SPeter Tyser 51784ad6884SPeter Tyser .align 5 51884ad6884SPeter Tysernot_used: 51984ad6884SPeter Tyser get_bad_stack 52084ad6884SPeter Tyser bad_save_user_regs 52184ad6884SPeter Tyser bl do_not_used 52284ad6884SPeter Tyser 52384ad6884SPeter Tyser#ifdef CONFIG_USE_IRQ 52484ad6884SPeter Tyser 52584ad6884SPeter Tyser .align 5 52684ad6884SPeter Tyserirq: 52784ad6884SPeter Tyser get_irq_stack 52884ad6884SPeter Tyser irq_save_user_regs 52984ad6884SPeter Tyser bl do_irq 53084ad6884SPeter Tyser irq_restore_user_regs 53184ad6884SPeter Tyser 53284ad6884SPeter Tyser .align 5 53384ad6884SPeter Tyserfiq: 53484ad6884SPeter Tyser get_fiq_stack 53584ad6884SPeter Tyser /* someone ought to write a more effiction fiq_save_user_regs */ 53684ad6884SPeter Tyser irq_save_user_regs 53784ad6884SPeter Tyser bl do_fiq 53884ad6884SPeter Tyser irq_restore_user_regs 53984ad6884SPeter Tyser 54084ad6884SPeter Tyser#else 54184ad6884SPeter Tyser 54284ad6884SPeter Tyser .align 5 54384ad6884SPeter Tyserirq: 54484ad6884SPeter Tyser get_bad_stack 54584ad6884SPeter Tyser bad_save_user_regs 54684ad6884SPeter Tyser bl do_irq 54784ad6884SPeter Tyser 54884ad6884SPeter Tyser .align 5 54984ad6884SPeter Tyserfiq: 55084ad6884SPeter Tyser get_bad_stack 55184ad6884SPeter Tyser bad_save_user_regs 55284ad6884SPeter Tyser bl do_fiq 55384ad6884SPeter Tyser 55484ad6884SPeter Tyser#endif 555401bb30bSAneesh V#endif /* CONFIG_SPL_BUILD */ 556