184ad6884SPeter Tyser/* 284ad6884SPeter Tyser * armboot - Startup Code for ARM926EJS CPU-core 384ad6884SPeter Tyser * 484ad6884SPeter Tyser * Copyright (c) 2003 Texas Instruments 584ad6884SPeter Tyser * 684ad6884SPeter Tyser * ----- Adapted for OMAP1610 OMAP730 from ARM925t code ------ 784ad6884SPeter Tyser * 8fa82f871SAlbert ARIBAUD * Copyright (c) 2001 Marius Gröger <mag@sysgo.de> 9fa82f871SAlbert ARIBAUD * Copyright (c) 2002 Alex Züpke <azu@sysgo.de> 1084ad6884SPeter Tyser * Copyright (c) 2002 Gary Jennejohn <garyj@denx.de> 1184ad6884SPeter Tyser * Copyright (c) 2003 Richard Woodruff <r-woodruff2@ti.com> 1284ad6884SPeter Tyser * Copyright (c) 2003 Kshitij <kshitij@ti.com> 1357b4bce9SAlbert ARIBAUD * Copyright (c) 2010 Albert Aribaud <albert.u.boot@aribaud.net> 1484ad6884SPeter Tyser * 151a459660SWolfgang Denk * SPDX-License-Identifier: GPL-2.0+ 1684ad6884SPeter Tyser */ 1784ad6884SPeter Tyser 1825ddd1fbSWolfgang Denk#include <asm-offsets.h> 1984ad6884SPeter Tyser#include <config.h> 2084ad6884SPeter Tyser#include <common.h> 2184ad6884SPeter Tyser 2284ad6884SPeter Tyser/* 2384ad6884SPeter Tyser ************************************************************************* 2484ad6884SPeter Tyser * 2584ad6884SPeter Tyser * Startup Code (reset vector) 2684ad6884SPeter Tyser * 2784ad6884SPeter Tyser * do important init only if we don't start from memory! 2884ad6884SPeter Tyser * setup Memory and board specific bits prior to relocation. 2984ad6884SPeter Tyser * relocate armboot to ram 3084ad6884SPeter Tyser * setup stack 3184ad6884SPeter Tyser * 3284ad6884SPeter Tyser ************************************************************************* 3384ad6884SPeter Tyser */ 3484ad6884SPeter Tyser 3541623c91SAlbert ARIBAUD .globl reset 36ab86f72cSHeiko Schocher 37ab86f72cSHeiko Schocherreset: 38ab86f72cSHeiko Schocher /* 39ab86f72cSHeiko Schocher * set the cpu to SVC32 mode 40ab86f72cSHeiko Schocher */ 41ab86f72cSHeiko Schocher mrs r0,cpsr 42ab86f72cSHeiko Schocher bic r0,r0,#0x1f 43ab86f72cSHeiko Schocher orr r0,r0,#0xd3 44ab86f72cSHeiko Schocher msr cpsr,r0 45ab86f72cSHeiko Schocher 46ab86f72cSHeiko Schocher /* 47ab86f72cSHeiko Schocher * we do sys-critical inits only at reboot, 48ab86f72cSHeiko Schocher * not when booting from ram! 49ab86f72cSHeiko Schocher */ 5027b66622SChristian Riesch#ifndef CONFIG_SKIP_LOWLEVEL_INIT 51ab86f72cSHeiko Schocher bl cpu_init_crit 5227b66622SChristian Riesch#endif 53ab86f72cSHeiko Schocher 54e05e5de7SAlbert ARIBAUD bl _main 55ab86f72cSHeiko Schocher 56ab86f72cSHeiko Schocher/*------------------------------------------------------------------------------*/ 57ab86f72cSHeiko Schocher 58e05e5de7SAlbert ARIBAUD .globl c_runtime_cpu_setup 59e05e5de7SAlbert ARIBAUDc_runtime_cpu_setup: 60e05e5de7SAlbert ARIBAUD 61e05e5de7SAlbert ARIBAUD bx lr 62e05e5de7SAlbert ARIBAUD 6384ad6884SPeter Tyser/* 6484ad6884SPeter Tyser ************************************************************************* 6584ad6884SPeter Tyser * 6684ad6884SPeter Tyser * CPU_init_critical registers 6784ad6884SPeter Tyser * 6884ad6884SPeter Tyser * setup important registers 6984ad6884SPeter Tyser * setup memory timing 7084ad6884SPeter Tyser * 7184ad6884SPeter Tyser ************************************************************************* 7284ad6884SPeter Tyser */ 7327b66622SChristian Riesch#ifndef CONFIG_SKIP_LOWLEVEL_INIT 7484ad6884SPeter Tysercpu_init_crit: 7584ad6884SPeter Tyser /* 76da104e04SSughosh Ganu * flush D cache before disabling it 7784ad6884SPeter Tyser */ 7884ad6884SPeter Tyser mov r0, #0 79da104e04SSughosh Ganuflush_dcache: 80da104e04SSughosh Ganu mrc p15, 0, r15, c7, c10, 3 81da104e04SSughosh Ganu bne flush_dcache 82da104e04SSughosh Ganu 83da104e04SSughosh Ganu mcr p15, 0, r0, c8, c7, 0 /* invalidate TLB */ 84da104e04SSughosh Ganu mcr p15, 0, r0, c7, c5, 0 /* invalidate I Cache */ 8584ad6884SPeter Tyser 8684ad6884SPeter Tyser /* 87d735a99dSChristian Riesch * disable MMU and D cache 88d735a99dSChristian Riesch * enable I cache if CONFIG_SYS_ICACHE_OFF is not defined 8984ad6884SPeter Tyser */ 9084ad6884SPeter Tyser mrc p15, 0, r0, c1, c0, 0 91b67d8816SChristian Riesch bic r0, r0, #0x00000300 /* clear bits 9:8 (---- --RS) */ 9284ad6884SPeter Tyser bic r0, r0, #0x00000087 /* clear bits 7, 2:0 (B--- -CAM) */ 93b67d8816SChristian Riesch#ifdef CONFIG_SYS_EXCEPTION_VECTORS_HIGH 94b67d8816SChristian Riesch orr r0, r0, #0x00002000 /* set bit 13 (--V- ----) */ 95b67d8816SChristian Riesch#else 96b67d8816SChristian Riesch bic r0, r0, #0x00002000 /* clear bit 13 (--V- ----) */ 97b67d8816SChristian Riesch#endif 98ba10b852SYuichiro Goto orr r0, r0, #0x00000002 /* set bit 1 (A) Align */ 99d735a99dSChristian Riesch#ifndef CONFIG_SYS_ICACHE_OFF 10084ad6884SPeter Tyser orr r0, r0, #0x00001000 /* set bit 12 (I) I-Cache */ 101d735a99dSChristian Riesch#endif 10284ad6884SPeter Tyser mcr p15, 0, r0, c1, c0, 0 10384ad6884SPeter Tyser 104*b5bd0982SSimon Glass#ifndef CONFIG_SKIP_LOWLEVEL_INIT_ONLY 10584ad6884SPeter Tyser /* 10684ad6884SPeter Tyser * Go setup Memory and board specific bits prior to relocation. 10784ad6884SPeter Tyser */ 10884ad6884SPeter Tyser mov ip, lr /* perserve link reg across call */ 10984ad6884SPeter Tyser bl lowlevel_init /* go setup pll,mux,memory */ 11084ad6884SPeter Tyser mov lr, ip /* restore link */ 111*b5bd0982SSimon Glass#endif 112ca4b5580SHeiko Schocher mov pc, lr /* back to my caller */ 11327b66622SChristian Riesch#endif /* CONFIG_SKIP_LOWLEVEL_INIT */ 114