184ad6884SPeter Tyser/* 284ad6884SPeter Tyser * armboot - Startup Code for ARM926EJS CPU-core 384ad6884SPeter Tyser * 484ad6884SPeter Tyser * Copyright (c) 2003 Texas Instruments 584ad6884SPeter Tyser * 684ad6884SPeter Tyser * ----- Adapted for OMAP1610 OMAP730 from ARM925t code ------ 784ad6884SPeter Tyser * 8fa82f871SAlbert ARIBAUD * Copyright (c) 2001 Marius Gröger <mag@sysgo.de> 9fa82f871SAlbert ARIBAUD * Copyright (c) 2002 Alex Züpke <azu@sysgo.de> 1084ad6884SPeter Tyser * Copyright (c) 2002 Gary Jennejohn <garyj@denx.de> 1184ad6884SPeter Tyser * Copyright (c) 2003 Richard Woodruff <r-woodruff2@ti.com> 1284ad6884SPeter Tyser * Copyright (c) 2003 Kshitij <kshitij@ti.com> 1357b4bce9SAlbert ARIBAUD * Copyright (c) 2010 Albert Aribaud <albert.u.boot@aribaud.net> 1484ad6884SPeter Tyser * 1584ad6884SPeter Tyser * See file CREDITS for list of people who contributed to this 1684ad6884SPeter Tyser * project. 1784ad6884SPeter Tyser * 1884ad6884SPeter Tyser * This program is free software; you can redistribute it and/or 1984ad6884SPeter Tyser * modify it under the terms of the GNU General Public License as 2084ad6884SPeter Tyser * published by the Free Software Foundation; either version 2 of 2184ad6884SPeter Tyser * the License, or (at your option) any later version. 2284ad6884SPeter Tyser * 2384ad6884SPeter Tyser * This program is distributed in the hope that it will be useful, 2484ad6884SPeter Tyser * but WITHOUT ANY WARRANTY; without even the implied warranty of 2584ad6884SPeter Tyser * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 2684ad6884SPeter Tyser * GNU General Public License for more details. 2784ad6884SPeter Tyser * 2884ad6884SPeter Tyser * You should have received a copy of the GNU General Public License 2984ad6884SPeter Tyser * along with this program; if not, write to the Free Software 3084ad6884SPeter Tyser * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 3184ad6884SPeter Tyser * MA 02111-1307 USA 3284ad6884SPeter Tyser */ 3384ad6884SPeter Tyser 3425ddd1fbSWolfgang Denk#include <asm-offsets.h> 3584ad6884SPeter Tyser#include <config.h> 3684ad6884SPeter Tyser#include <common.h> 3784ad6884SPeter Tyser#include <version.h> 3884ad6884SPeter Tyser 3984ad6884SPeter Tyser#if defined(CONFIG_OMAP1610) 4084ad6884SPeter Tyser#include <./configs/omap1510.h> 4184ad6884SPeter Tyser#elif defined(CONFIG_OMAP730) 4284ad6884SPeter Tyser#include <./configs/omap730.h> 4384ad6884SPeter Tyser#endif 4484ad6884SPeter Tyser 4584ad6884SPeter Tyser/* 4684ad6884SPeter Tyser ************************************************************************* 4784ad6884SPeter Tyser * 4884ad6884SPeter Tyser * Jump vector table as in table 3.1 in [1] 4984ad6884SPeter Tyser * 5084ad6884SPeter Tyser ************************************************************************* 5184ad6884SPeter Tyser */ 5284ad6884SPeter Tyser 5384ad6884SPeter Tyser 54337c4333SHeiko Schocher#ifdef CONFIG_SYS_DV_NOR_BOOT_CFG 55337c4333SHeiko Schocher.globl _start 56337c4333SHeiko Schocher_start: 57337c4333SHeiko Schocher.globl _NOR_BOOT_CFG 58337c4333SHeiko Schocher_NOR_BOOT_CFG: 59337c4333SHeiko Schocher .word CONFIG_SYS_DV_NOR_BOOT_CFG 60337c4333SHeiko Schocher b reset 61337c4333SHeiko Schocher#else 6284ad6884SPeter Tyser.globl _start 6384ad6884SPeter Tyser_start: 6484ad6884SPeter Tyser b reset 65337c4333SHeiko Schocher#endif 66401bb30bSAneesh V#ifdef CONFIG_SPL_BUILD 6784ad6884SPeter Tyser/* No exception handlers in preloader */ 6884ad6884SPeter Tyser ldr pc, _hang 6984ad6884SPeter Tyser ldr pc, _hang 7084ad6884SPeter Tyser ldr pc, _hang 7184ad6884SPeter Tyser ldr pc, _hang 7284ad6884SPeter Tyser ldr pc, _hang 7384ad6884SPeter Tyser ldr pc, _hang 7484ad6884SPeter Tyser ldr pc, _hang 7584ad6884SPeter Tyser 7684ad6884SPeter Tyser_hang: 7784ad6884SPeter Tyser .word do_hang 7884ad6884SPeter Tyser/* pad to 64 byte boundary */ 7984ad6884SPeter Tyser .word 0x12345678 8084ad6884SPeter Tyser .word 0x12345678 8184ad6884SPeter Tyser .word 0x12345678 8284ad6884SPeter Tyser .word 0x12345678 8384ad6884SPeter Tyser .word 0x12345678 8484ad6884SPeter Tyser .word 0x12345678 8584ad6884SPeter Tyser .word 0x12345678 8684ad6884SPeter Tyser#else 8784ad6884SPeter Tyser ldr pc, _undefined_instruction 8884ad6884SPeter Tyser ldr pc, _software_interrupt 8984ad6884SPeter Tyser ldr pc, _prefetch_abort 9084ad6884SPeter Tyser ldr pc, _data_abort 9184ad6884SPeter Tyser ldr pc, _not_used 9284ad6884SPeter Tyser ldr pc, _irq 9384ad6884SPeter Tyser ldr pc, _fiq 9484ad6884SPeter Tyser 9584ad6884SPeter Tyser_undefined_instruction: 9684ad6884SPeter Tyser .word undefined_instruction 9784ad6884SPeter Tyser_software_interrupt: 9884ad6884SPeter Tyser .word software_interrupt 9984ad6884SPeter Tyser_prefetch_abort: 10084ad6884SPeter Tyser .word prefetch_abort 10184ad6884SPeter Tyser_data_abort: 10284ad6884SPeter Tyser .word data_abort 10384ad6884SPeter Tyser_not_used: 10484ad6884SPeter Tyser .word not_used 10584ad6884SPeter Tyser_irq: 10684ad6884SPeter Tyser .word irq 10784ad6884SPeter Tyser_fiq: 10884ad6884SPeter Tyser .word fiq 10984ad6884SPeter Tyser 110401bb30bSAneesh V#endif /* CONFIG_SPL_BUILD */ 11184ad6884SPeter Tyser .balignl 16,0xdeadbeef 11284ad6884SPeter Tyser 11384ad6884SPeter Tyser 11484ad6884SPeter Tyser/* 11584ad6884SPeter Tyser ************************************************************************* 11684ad6884SPeter Tyser * 11784ad6884SPeter Tyser * Startup Code (reset vector) 11884ad6884SPeter Tyser * 11984ad6884SPeter Tyser * do important init only if we don't start from memory! 12084ad6884SPeter Tyser * setup Memory and board specific bits prior to relocation. 12184ad6884SPeter Tyser * relocate armboot to ram 12284ad6884SPeter Tyser * setup stack 12384ad6884SPeter Tyser * 12484ad6884SPeter Tyser ************************************************************************* 12584ad6884SPeter Tyser */ 12684ad6884SPeter Tyser 127ab86f72cSHeiko Schocher.globl _TEXT_BASE 12884ad6884SPeter Tyser_TEXT_BASE: 129435199f3SHeiko Schocher#ifdef CONFIG_NAND_SPL /* deprecated, use instead CONFIG_SPL_BUILD */ 13014d0a02aSWolfgang Denk .word CONFIG_SYS_TEXT_BASE 131435199f3SHeiko Schocher#else 132435199f3SHeiko Schocher#ifdef CONFIG_SPL_BUILD 133435199f3SHeiko Schocher .word CONFIG_SPL_TEXT_BASE 134435199f3SHeiko Schocher#else 135435199f3SHeiko Schocher .word CONFIG_SYS_TEXT_BASE 136435199f3SHeiko Schocher#endif 137435199f3SHeiko Schocher#endif 13884ad6884SPeter Tyser 13984ad6884SPeter Tyser/* 14084ad6884SPeter Tyser * These are defined in the board-specific linker script. 14192d5ecbaSAlbert Aribaud * Subtracting _start from them lets the linker put their 14292d5ecbaSAlbert Aribaud * relative position in the executable instead of leaving 14392d5ecbaSAlbert Aribaud * them null. 14484ad6884SPeter Tyser */ 14592d5ecbaSAlbert Aribaud.globl _bss_start_ofs 14692d5ecbaSAlbert Aribaud_bss_start_ofs: 14792d5ecbaSAlbert Aribaud .word __bss_start - _start 14884ad6884SPeter Tyser 14992d5ecbaSAlbert Aribaud.globl _bss_end_ofs 15092d5ecbaSAlbert Aribaud_bss_end_ofs: 15144c6e659SPo-Yu Chuang .word __bss_end__ - _start 15284ad6884SPeter Tyser 153f326cbbaSPo-Yu Chuang.globl _end_ofs 154f326cbbaSPo-Yu Chuang_end_ofs: 155f326cbbaSPo-Yu Chuang .word _end - _start 156f326cbbaSPo-Yu Chuang 1576a6e1677SHeiko Schocher#ifdef CONFIG_NAND_U_BOOT 1586a6e1677SHeiko Schocher.globl _end 1596a6e1677SHeiko Schocher_end: 1606a6e1677SHeiko Schocher .word __bss_end__ 1616a6e1677SHeiko Schocher#endif 1626a6e1677SHeiko Schocher 16384ad6884SPeter Tyser#ifdef CONFIG_USE_IRQ 16484ad6884SPeter Tyser/* IRQ stack memory (calculated at run-time) */ 16584ad6884SPeter Tyser.globl IRQ_STACK_START 16684ad6884SPeter TyserIRQ_STACK_START: 16784ad6884SPeter Tyser .word 0x0badc0de 16884ad6884SPeter Tyser 16984ad6884SPeter Tyser/* IRQ stack memory (calculated at run-time) */ 17084ad6884SPeter Tyser.globl FIQ_STACK_START 17184ad6884SPeter TyserFIQ_STACK_START: 17284ad6884SPeter Tyser .word 0x0badc0de 17384ad6884SPeter Tyser#endif 17484ad6884SPeter Tyser 175ab86f72cSHeiko Schocher/* IRQ stack memory (calculated at run-time) + 8 bytes */ 176ab86f72cSHeiko Schocher.globl IRQ_STACK_START_IN 177ab86f72cSHeiko SchocherIRQ_STACK_START_IN: 178ab86f72cSHeiko Schocher .word 0x0badc0de 17984ad6884SPeter Tyser 180ab86f72cSHeiko Schocher/* 181ab86f72cSHeiko Schocher * the actual reset code 182ab86f72cSHeiko Schocher */ 183ab86f72cSHeiko Schocher 184ab86f72cSHeiko Schocherreset: 185ab86f72cSHeiko Schocher /* 186ab86f72cSHeiko Schocher * set the cpu to SVC32 mode 187ab86f72cSHeiko Schocher */ 188ab86f72cSHeiko Schocher mrs r0,cpsr 189ab86f72cSHeiko Schocher bic r0,r0,#0x1f 190ab86f72cSHeiko Schocher orr r0,r0,#0xd3 191ab86f72cSHeiko Schocher msr cpsr,r0 192ab86f72cSHeiko Schocher 193ab86f72cSHeiko Schocher /* 194ab86f72cSHeiko Schocher * we do sys-critical inits only at reboot, 195ab86f72cSHeiko Schocher * not when booting from ram! 196ab86f72cSHeiko Schocher */ 19727b66622SChristian Riesch#ifndef CONFIG_SKIP_LOWLEVEL_INIT 198ab86f72cSHeiko Schocher bl cpu_init_crit 19927b66622SChristian Riesch#endif 200ab86f72cSHeiko Schocher 201ab86f72cSHeiko Schocher/* Set stackpointer in internal RAM to call board_init_f */ 202ab86f72cSHeiko Schochercall_board_init_f: 203435199f3SHeiko Schocher#ifdef CONFIG_NAND_SPL /* deprecated, use instead CONFIG_SPL_BUILD */ 204ab86f72cSHeiko Schocher ldr sp, =(CONFIG_SYS_INIT_SP_ADDR) 205435199f3SHeiko Schocher#else 206435199f3SHeiko Schocher#ifdef CONFIG_SPL_BUILD 207435199f3SHeiko Schocher ldr sp, =(CONFIG_SPL_STACK) 208435199f3SHeiko Schocher#else 209435199f3SHeiko Schocher ldr sp, =(CONFIG_SYS_INIT_SP_ADDR) 210435199f3SHeiko Schocher#endif 211435199f3SHeiko Schocher#endif 212296cae73SHeiko Schocher bic sp, sp, #7 /* 8-byte alignment for ABI compliance */ 213ab86f72cSHeiko Schocher ldr r0,=0x00000000 214ab86f72cSHeiko Schocher bl board_init_f 215ab86f72cSHeiko Schocher 216ab86f72cSHeiko Schocher/*------------------------------------------------------------------------------*/ 217ab86f72cSHeiko Schocher 218*3f7f2414STom Rini#if !defined(CONFIG_SPL_BUILD) || defined(CONFIG_NAND_SPL) 219ab86f72cSHeiko Schocher/* 220ab86f72cSHeiko Schocher * void relocate_code (addr_sp, gd, addr_moni) 221ab86f72cSHeiko Schocher * 222ab86f72cSHeiko Schocher * This "function" does not return, instead it continues in RAM 223ab86f72cSHeiko Schocher * after relocating the monitor code. 224ab86f72cSHeiko Schocher * 225ab86f72cSHeiko Schocher */ 226ab86f72cSHeiko Schocher .globl relocate_code 227ab86f72cSHeiko Schocherrelocate_code: 228ab86f72cSHeiko Schocher mov r4, r0 /* save addr_sp */ 229ab86f72cSHeiko Schocher mov r5, r1 /* save addr of gd */ 230ab86f72cSHeiko Schocher mov r6, r2 /* save addr of destination */ 231ab86f72cSHeiko Schocher 232ab86f72cSHeiko Schocher /* Set up the stack */ 233ab86f72cSHeiko Schocherstack_setup: 234ab86f72cSHeiko Schocher mov sp, r4 235ab86f72cSHeiko Schocher 236ab86f72cSHeiko Schocher adr r0, _start 237435199f3SHeiko Schocher sub r9, r6, r0 /* r9 <- relocation offset */ 238a1a47d3cSAndreas Bießmann cmp r0, r6 239a1a47d3cSAndreas Bießmann beq clear_bss /* skip relocation */ 240a78fb68fSAndreas Bießmann mov r1, r6 /* r1 <- scratch for copy loop */ 24192d5ecbaSAlbert Aribaud ldr r3, _bss_start_ofs 24292d5ecbaSAlbert Aribaud add r2, r0, r3 /* r2 <- source end address */ 243ab86f72cSHeiko Schocher 244ab86f72cSHeiko Schochercopy_loop: 245ab86f72cSHeiko Schocher ldmia r0!, {r9-r10} /* copy from source address [r0] */ 246a78fb68fSAndreas Bießmann stmia r1!, {r9-r10} /* copy to target address [r1] */ 247da90d4ceSAlbert Aribaud cmp r0, r2 /* until source end address [r2] */ 248da90d4ceSAlbert Aribaud blo copy_loop 249ab86f72cSHeiko Schocher 250401bb30bSAneesh V#ifndef CONFIG_SPL_BUILD 25192d5ecbaSAlbert Aribaud /* 25292d5ecbaSAlbert Aribaud * fix .rel.dyn relocations 25392d5ecbaSAlbert Aribaud */ 25492d5ecbaSAlbert Aribaud ldr r0, _TEXT_BASE /* r0 <- Text base */ 255a78fb68fSAndreas Bießmann sub r9, r6, r0 /* r9 <- relocation offset */ 25692d5ecbaSAlbert Aribaud ldr r10, _dynsym_start_ofs /* r10 <- sym table ofs */ 25792d5ecbaSAlbert Aribaud add r10, r10, r0 /* r10 <- sym table in FLASH */ 25892d5ecbaSAlbert Aribaud ldr r2, _rel_dyn_start_ofs /* r2 <- rel dyn start ofs */ 25992d5ecbaSAlbert Aribaud add r2, r2, r0 /* r2 <- rel dyn start in FLASH */ 26092d5ecbaSAlbert Aribaud ldr r3, _rel_dyn_end_ofs /* r3 <- rel dyn end ofs */ 26192d5ecbaSAlbert Aribaud add r3, r3, r0 /* r3 <- rel dyn end in FLASH */ 262ab86f72cSHeiko Schocherfixloop: 26392d5ecbaSAlbert Aribaud ldr r0, [r2] /* r0 <- location to fix up, IN FLASH! */ 2648c0c2b90SGray Remlin add r0, r0, r9 /* r0 <- location to fix up in RAM */ 26592d5ecbaSAlbert Aribaud ldr r1, [r2, #4] 2661f52d89fSAndreas Bießmann and r7, r1, #0xff 2671f52d89fSAndreas Bießmann cmp r7, #23 /* relative fixup? */ 26892d5ecbaSAlbert Aribaud beq fixrel 2691f52d89fSAndreas Bießmann cmp r7, #2 /* absolute fixup? */ 27092d5ecbaSAlbert Aribaud beq fixabs 27192d5ecbaSAlbert Aribaud /* ignore unknown type of fixup */ 27292d5ecbaSAlbert Aribaud b fixnext 27392d5ecbaSAlbert Aribaudfixabs: 27492d5ecbaSAlbert Aribaud /* absolute fix: set location to (offset) symbol value */ 27592d5ecbaSAlbert Aribaud mov r1, r1, LSR #4 /* r1 <- symbol index in .dynsym */ 27692d5ecbaSAlbert Aribaud add r1, r10, r1 /* r1 <- address of symbol in table */ 27792d5ecbaSAlbert Aribaud ldr r1, [r1, #4] /* r1 <- symbol value */ 2783600945bSWolfgang Denk add r1, r1, r9 /* r1 <- relocated sym addr */ 27992d5ecbaSAlbert Aribaud b fixnext 28092d5ecbaSAlbert Aribaudfixrel: 28192d5ecbaSAlbert Aribaud /* relative fix: increase location by offset */ 28292d5ecbaSAlbert Aribaud ldr r1, [r0] 28392d5ecbaSAlbert Aribaud add r1, r1, r9 28492d5ecbaSAlbert Aribaudfixnext: 28592d5ecbaSAlbert Aribaud str r1, [r0] 28692d5ecbaSAlbert Aribaud add r2, r2, #8 /* each rel.dyn entry is 8 bytes */ 287ab86f72cSHeiko Schocher cmp r2, r3 28892d5ecbaSAlbert Aribaud blo fixloop 289ab86f72cSHeiko Schocher#endif 290ab86f72cSHeiko Schocher 291ab86f72cSHeiko Schocherclear_bss: 292435199f3SHeiko Schocher#ifdef CONFIG_SPL_BUILD 293435199f3SHeiko Schocher /* No relocation for SPL */ 294435199f3SHeiko Schocher ldr r0, =__bss_start 295435199f3SHeiko Schocher ldr r1, =__bss_end__ 296435199f3SHeiko Schocher#else 29792d5ecbaSAlbert Aribaud ldr r0, _bss_start_ofs 29892d5ecbaSAlbert Aribaud ldr r1, _bss_end_ofs 299a78fb68fSAndreas Bießmann mov r4, r6 /* reloc addr */ 300ab86f72cSHeiko Schocher add r0, r0, r4 301ab86f72cSHeiko Schocher add r1, r1, r4 302435199f3SHeiko Schocher#endif 303ab86f72cSHeiko Schocher mov r2, #0x00000000 /* clear */ 304ab86f72cSHeiko Schocher 3058f1da535SChristian Rieschclbss_l:cmp r0, r1 /* clear loop... */ 3068f1da535SChristian Riesch bhs clbss_e /* if reached end of bss, exit */ 3078f1da535SChristian Riesch str r2, [r0] 308ab86f72cSHeiko Schocher add r0, r0, #4 3098f1da535SChristian Riesch b clbss_l 3108f1da535SChristian Rieschclbss_e: 311ab86f72cSHeiko Schocher 312435199f3SHeiko Schocher#ifndef CONFIG_SPL_BUILD 313ab86f72cSHeiko Schocher bl coloured_LED_init 3142d3be7c4SJason Kridner bl red_led_on 315ab86f72cSHeiko Schocher#endif 316ab86f72cSHeiko Schocher 317ab86f72cSHeiko Schocher/* 318ab86f72cSHeiko Schocher * We are done. Do not return, instead branch to second part of board 319ab86f72cSHeiko Schocher * initialization, now running from RAM. 320ab86f72cSHeiko Schocher */ 321ab86f72cSHeiko Schocher#ifdef CONFIG_NAND_SPL 32292d5ecbaSAlbert Aribaud ldr r0, _nand_boot_ofs 3239710504dSHeiko Schocher mov pc, r0 324ab86f72cSHeiko Schocher 3259710504dSHeiko Schocher_nand_boot_ofs: 3269710504dSHeiko Schocher .word nand_boot 327ab86f72cSHeiko Schocher#else 32892d5ecbaSAlbert Aribaud ldr r0, _board_init_r_ofs 3296087f1a9SAlexander Stein ldr r1, _TEXT_BASE 330123fb7deSDarius Augulis add lr, r0, r1 331123fb7deSDarius Augulis add lr, lr, r9 332ab86f72cSHeiko Schocher /* setup parameters for board_init_r */ 333ab86f72cSHeiko Schocher mov r0, r5 /* gd_t */ 334a78fb68fSAndreas Bießmann mov r1, r6 /* dest_addr */ 335ab86f72cSHeiko Schocher /* jump to it ... */ 336ab86f72cSHeiko Schocher mov pc, lr 337ab86f72cSHeiko Schocher 33892d5ecbaSAlbert Aribaud_board_init_r_ofs: 33992d5ecbaSAlbert Aribaud .word board_init_r - _start 340ab86f72cSHeiko Schocher#endif 341ab86f72cSHeiko Schocher 34292d5ecbaSAlbert Aribaud_rel_dyn_start_ofs: 34392d5ecbaSAlbert Aribaud .word __rel_dyn_start - _start 34492d5ecbaSAlbert Aribaud_rel_dyn_end_ofs: 34592d5ecbaSAlbert Aribaud .word __rel_dyn_end - _start 34692d5ecbaSAlbert Aribaud_dynsym_start_ofs: 34792d5ecbaSAlbert Aribaud .word __dynsym_start - _start 348*3f7f2414STom Rini#endif 34992d5ecbaSAlbert Aribaud 35084ad6884SPeter Tyser/* 35184ad6884SPeter Tyser ************************************************************************* 35284ad6884SPeter Tyser * 35384ad6884SPeter Tyser * CPU_init_critical registers 35484ad6884SPeter Tyser * 35584ad6884SPeter Tyser * setup important registers 35684ad6884SPeter Tyser * setup memory timing 35784ad6884SPeter Tyser * 35884ad6884SPeter Tyser ************************************************************************* 35984ad6884SPeter Tyser */ 36027b66622SChristian Riesch#ifndef CONFIG_SKIP_LOWLEVEL_INIT 36184ad6884SPeter Tysercpu_init_crit: 36284ad6884SPeter Tyser /* 363da104e04SSughosh Ganu * flush D cache before disabling it 36484ad6884SPeter Tyser */ 36584ad6884SPeter Tyser mov r0, #0 366da104e04SSughosh Ganuflush_dcache: 367da104e04SSughosh Ganu mrc p15, 0, r15, c7, c10, 3 368da104e04SSughosh Ganu bne flush_dcache 369da104e04SSughosh Ganu 370da104e04SSughosh Ganu mcr p15, 0, r0, c8, c7, 0 /* invalidate TLB */ 371da104e04SSughosh Ganu mcr p15, 0, r0, c7, c5, 0 /* invalidate I Cache */ 37284ad6884SPeter Tyser 37384ad6884SPeter Tyser /* 374d735a99dSChristian Riesch * disable MMU and D cache 375d735a99dSChristian Riesch * enable I cache if CONFIG_SYS_ICACHE_OFF is not defined 37684ad6884SPeter Tyser */ 37784ad6884SPeter Tyser mrc p15, 0, r0, c1, c0, 0 378b67d8816SChristian Riesch bic r0, r0, #0x00000300 /* clear bits 9:8 (---- --RS) */ 37984ad6884SPeter Tyser bic r0, r0, #0x00000087 /* clear bits 7, 2:0 (B--- -CAM) */ 380b67d8816SChristian Riesch#ifdef CONFIG_SYS_EXCEPTION_VECTORS_HIGH 381b67d8816SChristian Riesch orr r0, r0, #0x00002000 /* set bit 13 (--V- ----) */ 382b67d8816SChristian Riesch#else 383b67d8816SChristian Riesch bic r0, r0, #0x00002000 /* clear bit 13 (--V- ----) */ 384b67d8816SChristian Riesch#endif 38584ad6884SPeter Tyser orr r0, r0, #0x00000002 /* set bit 2 (A) Align */ 386d735a99dSChristian Riesch#ifndef CONFIG_SYS_ICACHE_OFF 38784ad6884SPeter Tyser orr r0, r0, #0x00001000 /* set bit 12 (I) I-Cache */ 388d735a99dSChristian Riesch#endif 38984ad6884SPeter Tyser mcr p15, 0, r0, c1, c0, 0 39084ad6884SPeter Tyser 39184ad6884SPeter Tyser /* 39284ad6884SPeter Tyser * Go setup Memory and board specific bits prior to relocation. 39384ad6884SPeter Tyser */ 39484ad6884SPeter Tyser mov ip, lr /* perserve link reg across call */ 39584ad6884SPeter Tyser bl lowlevel_init /* go setup pll,mux,memory */ 39684ad6884SPeter Tyser mov lr, ip /* restore link */ 397ca4b5580SHeiko Schocher mov pc, lr /* back to my caller */ 39827b66622SChristian Riesch#endif /* CONFIG_SKIP_LOWLEVEL_INIT */ 39984ad6884SPeter Tyser 400401bb30bSAneesh V#ifndef CONFIG_SPL_BUILD 40184ad6884SPeter Tyser/* 40284ad6884SPeter Tyser ************************************************************************* 40384ad6884SPeter Tyser * 40484ad6884SPeter Tyser * Interrupt handling 40584ad6884SPeter Tyser * 40684ad6884SPeter Tyser ************************************************************************* 40784ad6884SPeter Tyser */ 40884ad6884SPeter Tyser 40984ad6884SPeter Tyser@ 41084ad6884SPeter Tyser@ IRQ stack frame. 41184ad6884SPeter Tyser@ 41284ad6884SPeter Tyser#define S_FRAME_SIZE 72 41384ad6884SPeter Tyser 41484ad6884SPeter Tyser#define S_OLD_R0 68 41584ad6884SPeter Tyser#define S_PSR 64 41684ad6884SPeter Tyser#define S_PC 60 41784ad6884SPeter Tyser#define S_LR 56 41884ad6884SPeter Tyser#define S_SP 52 41984ad6884SPeter Tyser 42084ad6884SPeter Tyser#define S_IP 48 42184ad6884SPeter Tyser#define S_FP 44 42284ad6884SPeter Tyser#define S_R10 40 42384ad6884SPeter Tyser#define S_R9 36 42484ad6884SPeter Tyser#define S_R8 32 42584ad6884SPeter Tyser#define S_R7 28 42684ad6884SPeter Tyser#define S_R6 24 42784ad6884SPeter Tyser#define S_R5 20 42884ad6884SPeter Tyser#define S_R4 16 42984ad6884SPeter Tyser#define S_R3 12 43084ad6884SPeter Tyser#define S_R2 8 43184ad6884SPeter Tyser#define S_R1 4 43284ad6884SPeter Tyser#define S_R0 0 43384ad6884SPeter Tyser 43484ad6884SPeter Tyser#define MODE_SVC 0x13 43584ad6884SPeter Tyser#define I_BIT 0x80 43684ad6884SPeter Tyser 43784ad6884SPeter Tyser/* 43884ad6884SPeter Tyser * use bad_save_user_regs for abort/prefetch/undef/swi ... 43984ad6884SPeter Tyser * use irq_save_user_regs / irq_restore_user_regs for IRQ/FIQ handling 44084ad6884SPeter Tyser */ 44184ad6884SPeter Tyser 44284ad6884SPeter Tyser .macro bad_save_user_regs 44384ad6884SPeter Tyser @ carve out a frame on current user stack 44484ad6884SPeter Tyser sub sp, sp, #S_FRAME_SIZE 44584ad6884SPeter Tyser stmia sp, {r0 - r12} @ Save user registers (now in svc mode) r0-r12 446ab86f72cSHeiko Schocher ldr r2, IRQ_STACK_START_IN 44784ad6884SPeter Tyser @ get values for "aborted" pc and cpsr (into parm regs) 44884ad6884SPeter Tyser ldmia r2, {r2 - r3} 44984ad6884SPeter Tyser add r0, sp, #S_FRAME_SIZE @ grab pointer to old stack 45084ad6884SPeter Tyser add r5, sp, #S_SP 45184ad6884SPeter Tyser mov r1, lr 45284ad6884SPeter Tyser stmia r5, {r0 - r3} @ save sp_SVC, lr_SVC, pc, cpsr 45384ad6884SPeter Tyser mov r0, sp @ save current stack into r0 (param register) 45484ad6884SPeter Tyser .endm 45584ad6884SPeter Tyser 45684ad6884SPeter Tyser .macro irq_save_user_regs 45784ad6884SPeter Tyser sub sp, sp, #S_FRAME_SIZE 45884ad6884SPeter Tyser stmia sp, {r0 - r12} @ Calling r0-r12 45984ad6884SPeter Tyser @ !!!! R8 NEEDS to be saved !!!! a reserved stack spot would be good. 46084ad6884SPeter Tyser add r8, sp, #S_PC 46184ad6884SPeter Tyser stmdb r8, {sp, lr}^ @ Calling SP, LR 46284ad6884SPeter Tyser str lr, [r8, #0] @ Save calling PC 46384ad6884SPeter Tyser mrs r6, spsr 46484ad6884SPeter Tyser str r6, [r8, #4] @ Save CPSR 46584ad6884SPeter Tyser str r0, [r8, #8] @ Save OLD_R0 46684ad6884SPeter Tyser mov r0, sp 46784ad6884SPeter Tyser .endm 46884ad6884SPeter Tyser 46984ad6884SPeter Tyser .macro irq_restore_user_regs 47084ad6884SPeter Tyser ldmia sp, {r0 - lr}^ @ Calling r0 - lr 47184ad6884SPeter Tyser mov r0, r0 47284ad6884SPeter Tyser ldr lr, [sp, #S_PC] @ Get PC 47384ad6884SPeter Tyser add sp, sp, #S_FRAME_SIZE 47484ad6884SPeter Tyser subs pc, lr, #4 @ return & move spsr_svc into cpsr 47584ad6884SPeter Tyser .endm 47684ad6884SPeter Tyser 47784ad6884SPeter Tyser .macro get_bad_stack 478ab86f72cSHeiko Schocher ldr r13, IRQ_STACK_START_IN @ setup our mode stack 47984ad6884SPeter Tyser 48084ad6884SPeter Tyser str lr, [r13] @ save caller lr in position 0 of saved stack 48184ad6884SPeter Tyser mrs lr, spsr @ get the spsr 48284ad6884SPeter Tyser str lr, [r13, #4] @ save spsr in position 1 of saved stack 48384ad6884SPeter Tyser mov r13, #MODE_SVC @ prepare SVC-Mode 48484ad6884SPeter Tyser @ msr spsr_c, r13 48584ad6884SPeter Tyser msr spsr, r13 @ switch modes, make sure moves will execute 48684ad6884SPeter Tyser mov lr, pc @ capture return pc 48784ad6884SPeter Tyser movs pc, lr @ jump to next instruction & switch modes. 48884ad6884SPeter Tyser .endm 48984ad6884SPeter Tyser 49084ad6884SPeter Tyser .macro get_irq_stack @ setup IRQ stack 49184ad6884SPeter Tyser ldr sp, IRQ_STACK_START 49284ad6884SPeter Tyser .endm 49384ad6884SPeter Tyser 49484ad6884SPeter Tyser .macro get_fiq_stack @ setup FIQ stack 49584ad6884SPeter Tyser ldr sp, FIQ_STACK_START 49684ad6884SPeter Tyser .endm 497401bb30bSAneesh V#endif /* CONFIG_SPL_BUILD */ 49884ad6884SPeter Tyser 49984ad6884SPeter Tyser/* 50084ad6884SPeter Tyser * exception handlers 50184ad6884SPeter Tyser */ 502401bb30bSAneesh V#ifdef CONFIG_SPL_BUILD 50384ad6884SPeter Tyser .align 5 50484ad6884SPeter Tyserdo_hang: 50584ad6884SPeter Tyser ldr sp, _TEXT_BASE /* switch to abort stack */ 50684ad6884SPeter Tyser1: 50784ad6884SPeter Tyser bl 1b /* hang and never return */ 508401bb30bSAneesh V#else /* !CONFIG_SPL_BUILD */ 50984ad6884SPeter Tyser .align 5 51084ad6884SPeter Tyserundefined_instruction: 51184ad6884SPeter Tyser get_bad_stack 51284ad6884SPeter Tyser bad_save_user_regs 51384ad6884SPeter Tyser bl do_undefined_instruction 51484ad6884SPeter Tyser 51584ad6884SPeter Tyser .align 5 51684ad6884SPeter Tysersoftware_interrupt: 51784ad6884SPeter Tyser get_bad_stack 51884ad6884SPeter Tyser bad_save_user_regs 51984ad6884SPeter Tyser bl do_software_interrupt 52084ad6884SPeter Tyser 52184ad6884SPeter Tyser .align 5 52284ad6884SPeter Tyserprefetch_abort: 52384ad6884SPeter Tyser get_bad_stack 52484ad6884SPeter Tyser bad_save_user_regs 52584ad6884SPeter Tyser bl do_prefetch_abort 52684ad6884SPeter Tyser 52784ad6884SPeter Tyser .align 5 52884ad6884SPeter Tyserdata_abort: 52984ad6884SPeter Tyser get_bad_stack 53084ad6884SPeter Tyser bad_save_user_regs 53184ad6884SPeter Tyser bl do_data_abort 53284ad6884SPeter Tyser 53384ad6884SPeter Tyser .align 5 53484ad6884SPeter Tysernot_used: 53584ad6884SPeter Tyser get_bad_stack 53684ad6884SPeter Tyser bad_save_user_regs 53784ad6884SPeter Tyser bl do_not_used 53884ad6884SPeter Tyser 53984ad6884SPeter Tyser#ifdef CONFIG_USE_IRQ 54084ad6884SPeter Tyser 54184ad6884SPeter Tyser .align 5 54284ad6884SPeter Tyserirq: 54384ad6884SPeter Tyser get_irq_stack 54484ad6884SPeter Tyser irq_save_user_regs 54584ad6884SPeter Tyser bl do_irq 54684ad6884SPeter Tyser irq_restore_user_regs 54784ad6884SPeter Tyser 54884ad6884SPeter Tyser .align 5 54984ad6884SPeter Tyserfiq: 55084ad6884SPeter Tyser get_fiq_stack 55184ad6884SPeter Tyser /* someone ought to write a more effiction fiq_save_user_regs */ 55284ad6884SPeter Tyser irq_save_user_regs 55384ad6884SPeter Tyser bl do_fiq 55484ad6884SPeter Tyser irq_restore_user_regs 55584ad6884SPeter Tyser 55684ad6884SPeter Tyser#else 55784ad6884SPeter Tyser 55884ad6884SPeter Tyser .align 5 55984ad6884SPeter Tyserirq: 56084ad6884SPeter Tyser get_bad_stack 56184ad6884SPeter Tyser bad_save_user_regs 56284ad6884SPeter Tyser bl do_irq 56384ad6884SPeter Tyser 56484ad6884SPeter Tyser .align 5 56584ad6884SPeter Tyserfiq: 56684ad6884SPeter Tyser get_bad_stack 56784ad6884SPeter Tyser bad_save_user_regs 56884ad6884SPeter Tyser bl do_fiq 56984ad6884SPeter Tyser 57084ad6884SPeter Tyser#endif 571401bb30bSAneesh V#endif /* CONFIG_SPL_BUILD */ 572