1/* 2 * armboot - Startup Code for ARM926EJS CPU-core 3 * 4 * Copyright (c) 2003 Texas Instruments 5 * 6 * ----- Adapted for OMAP1610 OMAP730 from ARM925t code ------ 7 * 8 * Copyright (c) 2001 Marius Gröger <mag@sysgo.de> 9 * Copyright (c) 2002 Alex Züpke <azu@sysgo.de> 10 * Copyright (c) 2002 Gary Jennejohn <garyj@denx.de> 11 * Copyright (c) 2003 Richard Woodruff <r-woodruff2@ti.com> 12 * Copyright (c) 2003 Kshitij <kshitij@ti.com> 13 * 14 * SPDX-License-Identifier: GPL-2.0+ 15 */ 16 17 18#include <config.h> 19 20.globl _start 21_start: 22 b reset 23 ldr pc, _undefined_instruction 24 ldr pc, _software_interrupt 25 ldr pc, _prefetch_abort 26 ldr pc, _data_abort 27 ldr pc, _not_used 28 ldr pc, _irq 29 ldr pc, _fiq 30 31_undefined_instruction: 32_software_interrupt: 33_prefetch_abort: 34_data_abort: 35_not_used: 36_irq: 37_fiq: 38 .word infinite_loop 39 40infinite_loop: 41 b infinite_loop 42 43/* 44 ************************************************************************* 45 * 46 * Startup Code (reset vector) 47 * 48 * Below are the critical initializations already taken place in BootROM. 49 * So, these are not taken care in Xloader 50 * 1. Relocation to RAM 51 * 2. Initializing stacks 52 * 53 ************************************************************************* 54 */ 55 56/* 57 * the actual reset code 58 */ 59 60reset: 61/* 62 * Xloader has to return back to BootROM in a few cases. 63 * eg. Ethernet boot, UART boot, USB boot 64 * Saving registers for returning back 65 */ 66 stmdb sp!, {r0-r12,r14} 67 bl cpu_init_crit 68/* 69 * Clearing bss area is not done in Xloader. 70 * BSS area lies in the DDR location which is not yet initialized 71 * bss is assumed to be uninitialized. 72 */ 73 bl spl_boot 74 ldmia sp!, {r0-r12,pc} 75 76/* 77 ************************************************************************* 78 * 79 * CPU_init_critical registers 80 * 81 * setup important registers 82 * setup memory timing 83 * 84 ************************************************************************* 85 */ 86cpu_init_crit: 87 /* 88 * flush v4 I/D caches 89 */ 90 mov r0, #0 91 mcr p15, 0, r0, c7, c7, 0 /* flush v3/v4 cache */ 92 mcr p15, 0, r0, c8, c7, 0 /* flush v4 TLB */ 93 94 /* 95 * enable instruction cache 96 */ 97 mrc p15, 0, r0, c1, c0, 0 98 orr r0, r0, #0x00001000 /* set bit 12 (I) I-Cache */ 99 mcr p15, 0, r0, c1, c0, 0 100 101 /* 102 * Go setup Memory and board specific bits prior to relocation. 103 */ 104 stmdb sp!, {lr} 105 bl lowlevel_init /* go setup pll,mux,memory */ 106 ldmia sp!, {pc} 107