xref: /openbmc/u-boot/arch/arm/cpu/arm926ejs/mxs/timer.c (revision da4cfa6b)
1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3  * Freescale i.MX28 timer driver
4  *
5  * Copyright (C) 2011 Marek Vasut <marek.vasut@gmail.com>
6  * on behalf of DENX Software Engineering GmbH
7  *
8  * Based on code from LTIB:
9  * (C) Copyright 2009-2010 Freescale Semiconductor, Inc.
10  */
11 
12 #include <common.h>
13 #include <asm/io.h>
14 #include <asm/arch/imx-regs.h>
15 #include <asm/arch/sys_proto.h>
16 
17 /* Maximum fixed count */
18 #if defined(CONFIG_MX23)
19 #define TIMER_LOAD_VAL 0xffff
20 #elif defined(CONFIG_MX28)
21 #define TIMER_LOAD_VAL 0xffffffff
22 #endif
23 
24 DECLARE_GLOBAL_DATA_PTR;
25 
26 #define timestamp (gd->arch.tbl)
27 #define lastdec (gd->arch.lastinc)
28 
29 /*
30  * This driver uses 1kHz clock source.
31  */
32 #define	MXS_INCREMENTER_HZ		1000
33 
34 static inline unsigned long tick_to_time(unsigned long tick)
35 {
36 	return tick / (MXS_INCREMENTER_HZ / CONFIG_SYS_HZ);
37 }
38 
39 static inline unsigned long time_to_tick(unsigned long time)
40 {
41 	return time * (MXS_INCREMENTER_HZ / CONFIG_SYS_HZ);
42 }
43 
44 /* Calculate how many ticks happen in "us" microseconds */
45 static inline unsigned long us_to_tick(unsigned long us)
46 {
47 	return (us * MXS_INCREMENTER_HZ) / 1000000;
48 }
49 
50 int timer_init(void)
51 {
52 	struct mxs_timrot_regs *timrot_regs =
53 		(struct mxs_timrot_regs *)MXS_TIMROT_BASE;
54 
55 	/* Reset Timers and Rotary Encoder module */
56 	mxs_reset_block(&timrot_regs->hw_timrot_rotctrl_reg);
57 
58 	/* Set fixed_count to 0 */
59 #if defined(CONFIG_MX23)
60 	writel(0, &timrot_regs->hw_timrot_timcount0);
61 #elif defined(CONFIG_MX28)
62 	writel(0, &timrot_regs->hw_timrot_fixed_count0);
63 #endif
64 
65 	/* Set UPDATE bit and 1Khz frequency */
66 	writel(TIMROT_TIMCTRLn_UPDATE | TIMROT_TIMCTRLn_RELOAD |
67 		TIMROT_TIMCTRLn_SELECT_1KHZ_XTAL,
68 		&timrot_regs->hw_timrot_timctrl0);
69 
70 	/* Set fixed_count to maximal value */
71 #if defined(CONFIG_MX23)
72 	writel(TIMER_LOAD_VAL - 1, &timrot_regs->hw_timrot_timcount0);
73 #elif defined(CONFIG_MX28)
74 	writel(TIMER_LOAD_VAL, &timrot_regs->hw_timrot_fixed_count0);
75 #endif
76 
77 	return 0;
78 }
79 
80 unsigned long long get_ticks(void)
81 {
82 	struct mxs_timrot_regs *timrot_regs =
83 		(struct mxs_timrot_regs *)MXS_TIMROT_BASE;
84 	uint32_t now;
85 
86 	/* Current tick value */
87 #if defined(CONFIG_MX23)
88 	/* Upper bits are the valid ones. */
89 	now = readl(&timrot_regs->hw_timrot_timcount0) >>
90 		TIMROT_RUNNING_COUNTn_RUNNING_COUNT_OFFSET;
91 #elif defined(CONFIG_MX28)
92 	now = readl(&timrot_regs->hw_timrot_running_count0);
93 #else
94 #error "Don't know how to read timrot_regs"
95 #endif
96 
97 	if (lastdec >= now) {
98 		/*
99 		 * normal mode (non roll)
100 		 * move stamp forward with absolut diff ticks
101 		 */
102 		timestamp += (lastdec - now);
103 	} else {
104 		/* we have rollover of decrementer */
105 		timestamp += (TIMER_LOAD_VAL - now) + lastdec;
106 
107 	}
108 	lastdec = now;
109 
110 	return timestamp;
111 }
112 
113 ulong get_timer(ulong base)
114 {
115 	return tick_to_time(get_ticks()) - base;
116 }
117 
118 /* We use the HW_DIGCTL_MICROSECONDS register for sub-millisecond timer. */
119 #define	MXS_HW_DIGCTL_MICROSECONDS	0x8001c0c0
120 
121 void __udelay(unsigned long usec)
122 {
123 	uint32_t old, new, incr;
124 	uint32_t counter = 0;
125 
126 	old = readl(MXS_HW_DIGCTL_MICROSECONDS);
127 
128 	while (counter < usec) {
129 		new = readl(MXS_HW_DIGCTL_MICROSECONDS);
130 
131 		/* Check if the timer wrapped. */
132 		if (new < old) {
133 			incr = 0xffffffff - old;
134 			incr += new;
135 		} else {
136 			incr = new - old;
137 		}
138 
139 		/*
140 		 * Check if we are close to the maximum time and the counter
141 		 * would wrap if incremented. If that's the case, break out
142 		 * from the loop as the requested delay time passed.
143 		 */
144 		if (counter + incr < counter)
145 			break;
146 
147 		counter += incr;
148 		old = new;
149 	}
150 }
151 
152 ulong get_tbclk(void)
153 {
154 	return MXS_INCREMENTER_HZ;
155 }
156