1/* 2 * armboot - Startup Code for ARM926EJS CPU-core 3 * 4 * Copyright (c) 2003 Texas Instruments 5 * 6 * ----- Adapted for OMAP1610 OMAP730 from ARM925t code ------ 7 * 8 * Copyright (c) 2001 Marius Groger <mag@sysgo.de> 9 * Copyright (c) 2002 Alex Zupke <azu@sysgo.de> 10 * Copyright (c) 2002 Gary Jennejohn <garyj@denx.de> 11 * Copyright (c) 2003 Richard Woodruff <r-woodruff2@ti.com> 12 * Copyright (c) 2003 Kshitij <kshitij@ti.com> 13 * Copyright (c) 2010 Albert Aribaud <albert.u.boot@aribaud.net> 14 * 15 * Change to support call back into iMX28 bootrom 16 * Copyright (c) 2011 Marek Vasut <marek.vasut@gmail.com> 17 * on behalf of DENX Software Engineering GmbH 18 * 19 * SPDX-License-Identifier: GPL-2.0+ 20 */ 21 22#include <asm-offsets.h> 23#include <config.h> 24#include <common.h> 25#include <version.h> 26 27/* 28 ************************************************************************* 29 * 30 * Startup Code (reset vector) 31 * 32 * do important init only if we don't start from memory! 33 * setup Memory and board specific bits prior to relocation. 34 * relocate armboot to ram 35 * setup stack 36 * 37 ************************************************************************* 38 */ 39 40 .globl reset 41reset: 42 /* 43 * If the CPU is configured in "Wait JTAG connection mode", the stack 44 * pointer is not configured and is zero. This will cause crash when 45 * trying to push data onto stack right below here. Load the SP and make 46 * it point to the end of OCRAM if the SP is zero. 47 */ 48 cmp sp, #0x00000000 49 ldreq sp, =CONFIG_SYS_INIT_SP_ADDR 50 51 /* 52 * Store all registers on old stack pointer, this will allow us later to 53 * return to the BootROM and let the BootROM load U-Boot into RAM. 54 * 55 * WARNING: Register r0 and r1 are used by the BootROM to pass data 56 * to the called code. Register r0 will contain arbitrary 57 * data that are set in the BootStream. In case this code 58 * was started with CALL instruction, register r1 will contain 59 * pointer to the return value this function can then set. 60 * The code below MUST NOT CHANGE register r0 and r1 ! 61 */ 62 push {r0-r12,r14} 63 64 /* Save control register c1 */ 65 mrc p15, 0, r2, c1, c0, 0 66 push {r2} 67 68 /* Set the cpu to SVC32 mode and store old CPSR register content. */ 69 mrs r2, cpsr 70 push {r2} 71 bic r2, r2, #0x1f 72 orr r2, r2, #0xd3 73 msr cpsr, r2 74 75 bl board_init_ll 76 77 /* Restore BootROM's CPU mode (especially FIQ). */ 78 pop {r2} 79 msr cpsr,r2 80 81 /* 82 * Restore c1 register. Especially set exception vector location 83 * back to BootROM space which is required by bootrom for USB boot. 84 */ 85 pop {r2} 86 mcr p15, 0, r2, c1, c0, 0 87 88 pop {r0-r12,r14} 89 90 /* 91 * In case this code was started by the CALL instruction, the register 92 * r0 is examined by the BootROM after this code returns. The value in 93 * r0 must be set to 0 to indicate successful return. 94 */ 95 mov r0, #0 96 97 bx lr 98