1 /* 2 * Freescale i.MX28 Boot PMIC init 3 * 4 * Copyright (C) 2011 Marek Vasut <marek.vasut@gmail.com> 5 * on behalf of DENX Software Engineering GmbH 6 * 7 * SPDX-License-Identifier: GPL-2.0+ 8 */ 9 10 #include <common.h> 11 #include <config.h> 12 #include <asm/io.h> 13 #include <asm/arch/imx-regs.h> 14 15 #include "mxs_init.h" 16 17 /** 18 * mxs_power_clock2xtal() - Switch CPU core clock source to 24MHz XTAL 19 * 20 * This function switches the CPU core clock from PLL to 24MHz XTAL 21 * oscilator. This is necessary if the PLL is being reconfigured to 22 * prevent crash of the CPU core. 23 */ 24 static void mxs_power_clock2xtal(void) 25 { 26 struct mxs_clkctrl_regs *clkctrl_regs = 27 (struct mxs_clkctrl_regs *)MXS_CLKCTRL_BASE; 28 29 /* Set XTAL as CPU reference clock */ 30 writel(CLKCTRL_CLKSEQ_BYPASS_CPU, 31 &clkctrl_regs->hw_clkctrl_clkseq_set); 32 } 33 34 /** 35 * mxs_power_clock2pll() - Switch CPU core clock source to PLL 36 * 37 * This function switches the CPU core clock from 24MHz XTAL oscilator 38 * to PLL. This can only be called once the PLL has re-locked and once 39 * the PLL is stable after reconfiguration. 40 */ 41 static void mxs_power_clock2pll(void) 42 { 43 struct mxs_clkctrl_regs *clkctrl_regs = 44 (struct mxs_clkctrl_regs *)MXS_CLKCTRL_BASE; 45 46 setbits_le32(&clkctrl_regs->hw_clkctrl_pll0ctrl0, 47 CLKCTRL_PLL0CTRL0_POWER); 48 early_delay(100); 49 setbits_le32(&clkctrl_regs->hw_clkctrl_clkseq, 50 CLKCTRL_CLKSEQ_BYPASS_CPU); 51 } 52 53 /** 54 * mxs_power_set_auto_restart() - Set the auto-restart bit 55 * 56 * This function ungates the RTC block and sets the AUTO_RESTART 57 * bit to work around a design bug on MX28EVK Rev. A . 58 */ 59 60 static void mxs_power_set_auto_restart(void) 61 { 62 struct mxs_rtc_regs *rtc_regs = 63 (struct mxs_rtc_regs *)MXS_RTC_BASE; 64 65 writel(RTC_CTRL_SFTRST, &rtc_regs->hw_rtc_ctrl_clr); 66 while (readl(&rtc_regs->hw_rtc_ctrl) & RTC_CTRL_SFTRST) 67 ; 68 69 writel(RTC_CTRL_CLKGATE, &rtc_regs->hw_rtc_ctrl_clr); 70 while (readl(&rtc_regs->hw_rtc_ctrl) & RTC_CTRL_CLKGATE) 71 ; 72 73 /* Do nothing if flag already set */ 74 if (readl(&rtc_regs->hw_rtc_persistent0) & RTC_PERSISTENT0_AUTO_RESTART) 75 return; 76 77 while (readl(&rtc_regs->hw_rtc_stat) & RTC_STAT_NEW_REGS_MASK) 78 ; 79 80 setbits_le32(&rtc_regs->hw_rtc_persistent0, 81 RTC_PERSISTENT0_AUTO_RESTART); 82 writel(RTC_CTRL_FORCE_UPDATE, &rtc_regs->hw_rtc_ctrl_set); 83 writel(RTC_CTRL_FORCE_UPDATE, &rtc_regs->hw_rtc_ctrl_clr); 84 while (readl(&rtc_regs->hw_rtc_stat) & RTC_STAT_NEW_REGS_MASK) 85 ; 86 while (readl(&rtc_regs->hw_rtc_stat) & RTC_STAT_STALE_REGS_MASK) 87 ; 88 } 89 90 /** 91 * mxs_power_set_linreg() - Set linear regulators 25mV below DC-DC converter 92 * 93 * This function configures the VDDIO, VDDA and VDDD linear regulators output 94 * to be 25mV below the VDDIO, VDDA and VDDD output from the DC-DC switching 95 * converter. This is the recommended setting for the case where we use both 96 * linear regulators and DC-DC converter to power the VDDIO rail. 97 */ 98 static void mxs_power_set_linreg(void) 99 { 100 struct mxs_power_regs *power_regs = 101 (struct mxs_power_regs *)MXS_POWER_BASE; 102 103 /* Set linear regulator 25mV below switching converter */ 104 clrsetbits_le32(&power_regs->hw_power_vdddctrl, 105 POWER_VDDDCTRL_LINREG_OFFSET_MASK, 106 POWER_VDDDCTRL_LINREG_OFFSET_1STEPS_BELOW); 107 108 clrsetbits_le32(&power_regs->hw_power_vddactrl, 109 POWER_VDDACTRL_LINREG_OFFSET_MASK, 110 POWER_VDDACTRL_LINREG_OFFSET_1STEPS_BELOW); 111 112 clrsetbits_le32(&power_regs->hw_power_vddioctrl, 113 POWER_VDDIOCTRL_LINREG_OFFSET_MASK, 114 POWER_VDDIOCTRL_LINREG_OFFSET_1STEPS_BELOW); 115 } 116 117 /** 118 * mxs_get_batt_volt() - Measure battery input voltage 119 * 120 * This function retrieves the battery input voltage and returns it. 121 */ 122 static int mxs_get_batt_volt(void) 123 { 124 struct mxs_power_regs *power_regs = 125 (struct mxs_power_regs *)MXS_POWER_BASE; 126 uint32_t volt = readl(&power_regs->hw_power_battmonitor); 127 volt &= POWER_BATTMONITOR_BATT_VAL_MASK; 128 volt >>= POWER_BATTMONITOR_BATT_VAL_OFFSET; 129 volt *= 8; 130 return volt; 131 } 132 133 /** 134 * mxs_is_batt_ready() - Test if the battery provides enough voltage to boot 135 * 136 * This function checks if the battery input voltage is higher than 3.6V and 137 * therefore allows the system to successfully boot using this power source. 138 */ 139 static int mxs_is_batt_ready(void) 140 { 141 return (mxs_get_batt_volt() >= 3600); 142 } 143 144 /** 145 * mxs_is_batt_good() - Test if battery is operational at all 146 * 147 * This function starts recharging the battery and tests if the input current 148 * provided by the 5V input recharging the battery is also sufficient to power 149 * the DC-DC converter. 150 */ 151 static int mxs_is_batt_good(void) 152 { 153 struct mxs_power_regs *power_regs = 154 (struct mxs_power_regs *)MXS_POWER_BASE; 155 uint32_t volt = mxs_get_batt_volt(); 156 157 if ((volt >= 2400) && (volt <= 4300)) 158 return 1; 159 160 clrsetbits_le32(&power_regs->hw_power_5vctrl, 161 POWER_5VCTRL_CHARGE_4P2_ILIMIT_MASK, 162 0x3 << POWER_5VCTRL_CHARGE_4P2_ILIMIT_OFFSET); 163 writel(POWER_5VCTRL_PWD_CHARGE_4P2_MASK, 164 &power_regs->hw_power_5vctrl_clr); 165 166 clrsetbits_le32(&power_regs->hw_power_charge, 167 POWER_CHARGE_STOP_ILIMIT_MASK | POWER_CHARGE_BATTCHRG_I_MASK, 168 POWER_CHARGE_STOP_ILIMIT_10MA | 0x3); 169 170 writel(POWER_CHARGE_PWD_BATTCHRG, &power_regs->hw_power_charge_clr); 171 writel(POWER_5VCTRL_PWD_CHARGE_4P2_MASK, 172 &power_regs->hw_power_5vctrl_clr); 173 174 early_delay(500000); 175 176 volt = mxs_get_batt_volt(); 177 178 if (volt >= 3500) 179 return 0; 180 181 if (volt >= 2400) 182 return 1; 183 184 writel(POWER_CHARGE_STOP_ILIMIT_MASK | POWER_CHARGE_BATTCHRG_I_MASK, 185 &power_regs->hw_power_charge_clr); 186 writel(POWER_CHARGE_PWD_BATTCHRG, &power_regs->hw_power_charge_set); 187 188 return 0; 189 } 190 191 /** 192 * mxs_power_setup_5v_detect() - Start the 5V input detection comparator 193 * 194 * This function enables the 5V detection comparator and sets the 5V valid 195 * threshold to 4.4V . We use 4.4V threshold here to make sure that even 196 * under high load, the voltage drop on the 5V input won't be so critical 197 * to cause undervolt on the 4P2 linear regulator supplying the DC-DC 198 * converter and thus making the system crash. 199 */ 200 static void mxs_power_setup_5v_detect(void) 201 { 202 struct mxs_power_regs *power_regs = 203 (struct mxs_power_regs *)MXS_POWER_BASE; 204 205 /* Start 5V detection */ 206 clrsetbits_le32(&power_regs->hw_power_5vctrl, 207 POWER_5VCTRL_VBUSVALID_TRSH_MASK, 208 POWER_5VCTRL_VBUSVALID_TRSH_4V4 | 209 POWER_5VCTRL_PWRUP_VBUS_CMPS); 210 } 211 212 /** 213 * mxs_src_power_init() - Preconfigure the power block 214 * 215 * This function configures reasonable values for the DC-DC control loop 216 * and battery monitor. 217 */ 218 static void mxs_src_power_init(void) 219 { 220 struct mxs_power_regs *power_regs = 221 (struct mxs_power_regs *)MXS_POWER_BASE; 222 223 /* Improve efficieny and reduce transient ripple */ 224 writel(POWER_LOOPCTRL_TOGGLE_DIF | POWER_LOOPCTRL_EN_CM_HYST | 225 POWER_LOOPCTRL_EN_DF_HYST, &power_regs->hw_power_loopctrl_set); 226 227 clrsetbits_le32(&power_regs->hw_power_dclimits, 228 POWER_DCLIMITS_POSLIMIT_BUCK_MASK, 229 0x30 << POWER_DCLIMITS_POSLIMIT_BUCK_OFFSET); 230 231 setbits_le32(&power_regs->hw_power_battmonitor, 232 POWER_BATTMONITOR_EN_BATADJ); 233 234 /* Increase the RCSCALE level for quick DCDC response to dynamic load */ 235 clrsetbits_le32(&power_regs->hw_power_loopctrl, 236 POWER_LOOPCTRL_EN_RCSCALE_MASK, 237 POWER_LOOPCTRL_RCSCALE_THRESH | 238 POWER_LOOPCTRL_EN_RCSCALE_8X); 239 240 clrsetbits_le32(&power_regs->hw_power_minpwr, 241 POWER_MINPWR_HALFFETS, POWER_MINPWR_DOUBLE_FETS); 242 243 /* 5V to battery handoff ... FIXME */ 244 setbits_le32(&power_regs->hw_power_5vctrl, POWER_5VCTRL_DCDC_XFER); 245 early_delay(30); 246 clrbits_le32(&power_regs->hw_power_5vctrl, POWER_5VCTRL_DCDC_XFER); 247 } 248 249 /** 250 * mxs_power_init_4p2_params() - Configure the parameters of the 4P2 regulator 251 * 252 * This function configures the necessary parameters for the 4P2 linear 253 * regulator to supply the DC-DC converter from 5V input. 254 */ 255 static void mxs_power_init_4p2_params(void) 256 { 257 struct mxs_power_regs *power_regs = 258 (struct mxs_power_regs *)MXS_POWER_BASE; 259 260 /* Setup 4P2 parameters */ 261 clrsetbits_le32(&power_regs->hw_power_dcdc4p2, 262 POWER_DCDC4P2_CMPTRIP_MASK | POWER_DCDC4P2_TRG_MASK, 263 POWER_DCDC4P2_TRG_4V2 | (31 << POWER_DCDC4P2_CMPTRIP_OFFSET)); 264 265 clrsetbits_le32(&power_regs->hw_power_5vctrl, 266 POWER_5VCTRL_HEADROOM_ADJ_MASK, 267 0x4 << POWER_5VCTRL_HEADROOM_ADJ_OFFSET); 268 269 clrsetbits_le32(&power_regs->hw_power_dcdc4p2, 270 POWER_DCDC4P2_DROPOUT_CTRL_MASK, 271 POWER_DCDC4P2_DROPOUT_CTRL_100MV | 272 POWER_DCDC4P2_DROPOUT_CTRL_SRC_SEL); 273 274 clrsetbits_le32(&power_regs->hw_power_5vctrl, 275 POWER_5VCTRL_CHARGE_4P2_ILIMIT_MASK, 276 0x3f << POWER_5VCTRL_CHARGE_4P2_ILIMIT_OFFSET); 277 } 278 279 /** 280 * mxs_enable_4p2_dcdc_input() - Enable or disable the DCDC input from 4P2 281 * @xfer: Select if the input shall be enabled or disabled 282 * 283 * This function enables or disables the 4P2 input into the DC-DC converter. 284 */ 285 static void mxs_enable_4p2_dcdc_input(int xfer) 286 { 287 struct mxs_power_regs *power_regs = 288 (struct mxs_power_regs *)MXS_POWER_BASE; 289 uint32_t tmp, vbus_thresh, vbus_5vdetect, pwd_bo; 290 uint32_t prev_5v_brnout, prev_5v_droop; 291 292 prev_5v_brnout = readl(&power_regs->hw_power_5vctrl) & 293 POWER_5VCTRL_PWDN_5VBRNOUT; 294 prev_5v_droop = readl(&power_regs->hw_power_ctrl) & 295 POWER_CTRL_ENIRQ_VDD5V_DROOP; 296 297 clrbits_le32(&power_regs->hw_power_5vctrl, POWER_5VCTRL_PWDN_5VBRNOUT); 298 writel(POWER_RESET_UNLOCK_KEY | POWER_RESET_PWD_OFF, 299 &power_regs->hw_power_reset); 300 301 clrbits_le32(&power_regs->hw_power_ctrl, POWER_CTRL_ENIRQ_VDD5V_DROOP); 302 303 if (xfer && (readl(&power_regs->hw_power_5vctrl) & 304 POWER_5VCTRL_ENABLE_DCDC)) { 305 return; 306 } 307 308 /* 309 * Recording orignal values that will be modified temporarlily 310 * to handle a chip bug. See chip errata for CQ ENGR00115837 311 */ 312 tmp = readl(&power_regs->hw_power_5vctrl); 313 vbus_thresh = tmp & POWER_5VCTRL_VBUSVALID_TRSH_MASK; 314 vbus_5vdetect = tmp & POWER_5VCTRL_VBUSVALID_5VDETECT; 315 316 pwd_bo = readl(&power_regs->hw_power_minpwr) & POWER_MINPWR_PWD_BO; 317 318 /* 319 * Disable mechanisms that get erroneously tripped by when setting 320 * the DCDC4P2 EN_DCDC 321 */ 322 clrbits_le32(&power_regs->hw_power_5vctrl, 323 POWER_5VCTRL_VBUSVALID_5VDETECT | 324 POWER_5VCTRL_VBUSVALID_TRSH_MASK); 325 326 writel(POWER_MINPWR_PWD_BO, &power_regs->hw_power_minpwr_set); 327 328 if (xfer) { 329 setbits_le32(&power_regs->hw_power_5vctrl, 330 POWER_5VCTRL_DCDC_XFER); 331 early_delay(20); 332 clrbits_le32(&power_regs->hw_power_5vctrl, 333 POWER_5VCTRL_DCDC_XFER); 334 335 setbits_le32(&power_regs->hw_power_5vctrl, 336 POWER_5VCTRL_ENABLE_DCDC); 337 } else { 338 setbits_le32(&power_regs->hw_power_dcdc4p2, 339 POWER_DCDC4P2_ENABLE_DCDC); 340 } 341 342 early_delay(25); 343 344 clrsetbits_le32(&power_regs->hw_power_5vctrl, 345 POWER_5VCTRL_VBUSVALID_TRSH_MASK, vbus_thresh); 346 347 if (vbus_5vdetect) 348 writel(vbus_5vdetect, &power_regs->hw_power_5vctrl_set); 349 350 if (!pwd_bo) 351 clrbits_le32(&power_regs->hw_power_minpwr, POWER_MINPWR_PWD_BO); 352 353 while (readl(&power_regs->hw_power_ctrl) & POWER_CTRL_VBUS_VALID_IRQ) 354 writel(POWER_CTRL_VBUS_VALID_IRQ, 355 &power_regs->hw_power_ctrl_clr); 356 357 if (prev_5v_brnout) { 358 writel(POWER_5VCTRL_PWDN_5VBRNOUT, 359 &power_regs->hw_power_5vctrl_set); 360 writel(POWER_RESET_UNLOCK_KEY, 361 &power_regs->hw_power_reset); 362 } else { 363 writel(POWER_5VCTRL_PWDN_5VBRNOUT, 364 &power_regs->hw_power_5vctrl_clr); 365 writel(POWER_RESET_UNLOCK_KEY | POWER_RESET_PWD_OFF, 366 &power_regs->hw_power_reset); 367 } 368 369 while (readl(&power_regs->hw_power_ctrl) & POWER_CTRL_VDD5V_DROOP_IRQ) 370 writel(POWER_CTRL_VDD5V_DROOP_IRQ, 371 &power_regs->hw_power_ctrl_clr); 372 373 if (prev_5v_droop) 374 clrbits_le32(&power_regs->hw_power_ctrl, 375 POWER_CTRL_ENIRQ_VDD5V_DROOP); 376 else 377 setbits_le32(&power_regs->hw_power_ctrl, 378 POWER_CTRL_ENIRQ_VDD5V_DROOP); 379 } 380 381 /** 382 * mxs_power_init_4p2_regulator() - Start the 4P2 regulator 383 * 384 * This function enables the 4P2 regulator and switches the DC-DC converter 385 * to use the 4P2 input. 386 */ 387 static void mxs_power_init_4p2_regulator(void) 388 { 389 struct mxs_power_regs *power_regs = 390 (struct mxs_power_regs *)MXS_POWER_BASE; 391 uint32_t tmp, tmp2; 392 393 setbits_le32(&power_regs->hw_power_dcdc4p2, POWER_DCDC4P2_ENABLE_4P2); 394 395 writel(POWER_CHARGE_ENABLE_LOAD, &power_regs->hw_power_charge_set); 396 397 writel(POWER_5VCTRL_CHARGE_4P2_ILIMIT_MASK, 398 &power_regs->hw_power_5vctrl_clr); 399 clrbits_le32(&power_regs->hw_power_dcdc4p2, POWER_DCDC4P2_TRG_MASK); 400 401 /* Power up the 4p2 rail and logic/control */ 402 writel(POWER_5VCTRL_PWD_CHARGE_4P2_MASK, 403 &power_regs->hw_power_5vctrl_clr); 404 405 /* 406 * Start charging up the 4p2 capacitor. We ramp of this charge 407 * gradually to avoid large inrush current from the 5V cable which can 408 * cause transients/problems 409 */ 410 mxs_enable_4p2_dcdc_input(0); 411 412 if (readl(&power_regs->hw_power_ctrl) & POWER_CTRL_VBUS_VALID_IRQ) { 413 /* 414 * If we arrived here, we were unable to recover from mx23 chip 415 * errata 5837. 4P2 is disabled and sufficient battery power is 416 * not present. Exiting to not enable DCDC power during 5V 417 * connected state. 418 */ 419 clrbits_le32(&power_regs->hw_power_dcdc4p2, 420 POWER_DCDC4P2_ENABLE_DCDC); 421 writel(POWER_5VCTRL_PWD_CHARGE_4P2_MASK, 422 &power_regs->hw_power_5vctrl_set); 423 hang(); 424 } 425 426 /* 427 * Here we set the 4p2 brownout level to something very close to 4.2V. 428 * We then check the brownout status. If the brownout status is false, 429 * the voltage is already close to the target voltage of 4.2V so we 430 * can go ahead and set the 4P2 current limit to our max target limit. 431 * If the brownout status is true, we need to ramp us the current limit 432 * so that we don't cause large inrush current issues. We step up the 433 * current limit until the brownout status is false or until we've 434 * reached our maximum defined 4p2 current limit. 435 */ 436 clrsetbits_le32(&power_regs->hw_power_dcdc4p2, 437 POWER_DCDC4P2_BO_MASK, 438 22 << POWER_DCDC4P2_BO_OFFSET); /* 4.15V */ 439 440 if (!(readl(&power_regs->hw_power_sts) & POWER_STS_DCDC_4P2_BO)) { 441 setbits_le32(&power_regs->hw_power_5vctrl, 442 0x3f << POWER_5VCTRL_CHARGE_4P2_ILIMIT_OFFSET); 443 } else { 444 tmp = (readl(&power_regs->hw_power_5vctrl) & 445 POWER_5VCTRL_CHARGE_4P2_ILIMIT_MASK) >> 446 POWER_5VCTRL_CHARGE_4P2_ILIMIT_OFFSET; 447 while (tmp < 0x3f) { 448 if (!(readl(&power_regs->hw_power_sts) & 449 POWER_STS_DCDC_4P2_BO)) { 450 tmp = readl(&power_regs->hw_power_5vctrl); 451 tmp |= POWER_5VCTRL_CHARGE_4P2_ILIMIT_MASK; 452 early_delay(100); 453 writel(tmp, &power_regs->hw_power_5vctrl); 454 break; 455 } else { 456 tmp++; 457 tmp2 = readl(&power_regs->hw_power_5vctrl); 458 tmp2 &= ~POWER_5VCTRL_CHARGE_4P2_ILIMIT_MASK; 459 tmp2 |= tmp << 460 POWER_5VCTRL_CHARGE_4P2_ILIMIT_OFFSET; 461 writel(tmp2, &power_regs->hw_power_5vctrl); 462 early_delay(100); 463 } 464 } 465 } 466 467 clrbits_le32(&power_regs->hw_power_dcdc4p2, POWER_DCDC4P2_BO_MASK); 468 writel(POWER_CTRL_DCDC4P2_BO_IRQ, &power_regs->hw_power_ctrl_clr); 469 } 470 471 /** 472 * mxs_power_init_dcdc_4p2_source() - Switch DC-DC converter to 4P2 source 473 * 474 * This function configures the DC-DC converter to be supplied from the 4P2 475 * linear regulator. 476 */ 477 static void mxs_power_init_dcdc_4p2_source(void) 478 { 479 struct mxs_power_regs *power_regs = 480 (struct mxs_power_regs *)MXS_POWER_BASE; 481 482 if (!(readl(&power_regs->hw_power_dcdc4p2) & 483 POWER_DCDC4P2_ENABLE_DCDC)) { 484 hang(); 485 } 486 487 mxs_enable_4p2_dcdc_input(1); 488 489 if (readl(&power_regs->hw_power_ctrl) & POWER_CTRL_VBUS_VALID_IRQ) { 490 clrbits_le32(&power_regs->hw_power_dcdc4p2, 491 POWER_DCDC4P2_ENABLE_DCDC); 492 writel(POWER_5VCTRL_ENABLE_DCDC, 493 &power_regs->hw_power_5vctrl_clr); 494 writel(POWER_5VCTRL_PWD_CHARGE_4P2_MASK, 495 &power_regs->hw_power_5vctrl_set); 496 } 497 } 498 499 /** 500 * mxs_power_enable_4p2() - Power up the 4P2 regulator 501 * 502 * This function drives the process of powering up the 4P2 linear regulator 503 * and switching the DC-DC converter input over to the 4P2 linear regulator. 504 */ 505 static void mxs_power_enable_4p2(void) 506 { 507 struct mxs_power_regs *power_regs = 508 (struct mxs_power_regs *)MXS_POWER_BASE; 509 uint32_t vdddctrl, vddactrl, vddioctrl; 510 uint32_t tmp; 511 512 vdddctrl = readl(&power_regs->hw_power_vdddctrl); 513 vddactrl = readl(&power_regs->hw_power_vddactrl); 514 vddioctrl = readl(&power_regs->hw_power_vddioctrl); 515 516 setbits_le32(&power_regs->hw_power_vdddctrl, 517 POWER_VDDDCTRL_DISABLE_FET | POWER_VDDDCTRL_ENABLE_LINREG | 518 POWER_VDDDCTRL_PWDN_BRNOUT); 519 520 setbits_le32(&power_regs->hw_power_vddactrl, 521 POWER_VDDACTRL_DISABLE_FET | POWER_VDDACTRL_ENABLE_LINREG | 522 POWER_VDDACTRL_PWDN_BRNOUT); 523 524 setbits_le32(&power_regs->hw_power_vddioctrl, 525 POWER_VDDIOCTRL_DISABLE_FET | POWER_VDDIOCTRL_PWDN_BRNOUT); 526 527 mxs_power_init_4p2_params(); 528 mxs_power_init_4p2_regulator(); 529 530 /* Shutdown battery (none present) */ 531 if (!mxs_is_batt_ready()) { 532 clrbits_le32(&power_regs->hw_power_dcdc4p2, 533 POWER_DCDC4P2_BO_MASK); 534 writel(POWER_CTRL_DCDC4P2_BO_IRQ, 535 &power_regs->hw_power_ctrl_clr); 536 writel(POWER_CTRL_ENIRQ_DCDC4P2_BO, 537 &power_regs->hw_power_ctrl_clr); 538 } 539 540 mxs_power_init_dcdc_4p2_source(); 541 542 writel(vdddctrl, &power_regs->hw_power_vdddctrl); 543 early_delay(20); 544 writel(vddactrl, &power_regs->hw_power_vddactrl); 545 early_delay(20); 546 writel(vddioctrl, &power_regs->hw_power_vddioctrl); 547 548 /* 549 * Check if FET is enabled on either powerout and if so, 550 * disable load. 551 */ 552 tmp = 0; 553 tmp |= !(readl(&power_regs->hw_power_vdddctrl) & 554 POWER_VDDDCTRL_DISABLE_FET); 555 tmp |= !(readl(&power_regs->hw_power_vddactrl) & 556 POWER_VDDACTRL_DISABLE_FET); 557 tmp |= !(readl(&power_regs->hw_power_vddioctrl) & 558 POWER_VDDIOCTRL_DISABLE_FET); 559 if (tmp) 560 writel(POWER_CHARGE_ENABLE_LOAD, 561 &power_regs->hw_power_charge_clr); 562 } 563 564 /** 565 * mxs_boot_valid_5v() - Boot from 5V supply 566 * 567 * This function configures the power block to boot from valid 5V input. 568 * This is called only if the 5V is reliable and can properly supply the 569 * CPU. This function proceeds to configure the 4P2 converter to be supplied 570 * from the 5V input. 571 */ 572 static void mxs_boot_valid_5v(void) 573 { 574 struct mxs_power_regs *power_regs = 575 (struct mxs_power_regs *)MXS_POWER_BASE; 576 577 /* 578 * Use VBUSVALID level instead of VDD5V_GT_VDDIO level to trigger a 5V 579 * disconnect event. FIXME 580 */ 581 writel(POWER_5VCTRL_VBUSVALID_5VDETECT, 582 &power_regs->hw_power_5vctrl_set); 583 584 /* Configure polarity to check for 5V disconnection. */ 585 writel(POWER_CTRL_POLARITY_VBUSVALID | 586 POWER_CTRL_POLARITY_VDD5V_GT_VDDIO, 587 &power_regs->hw_power_ctrl_clr); 588 589 writel(POWER_CTRL_VBUS_VALID_IRQ | POWER_CTRL_VDD5V_GT_VDDIO_IRQ, 590 &power_regs->hw_power_ctrl_clr); 591 592 mxs_power_enable_4p2(); 593 } 594 595 /** 596 * mxs_powerdown() - Shut down the system 597 * 598 * This function powers down the CPU completely. 599 */ 600 static void mxs_powerdown(void) 601 { 602 struct mxs_power_regs *power_regs = 603 (struct mxs_power_regs *)MXS_POWER_BASE; 604 writel(POWER_RESET_UNLOCK_KEY, &power_regs->hw_power_reset); 605 writel(POWER_RESET_UNLOCK_KEY | POWER_RESET_PWD_OFF, 606 &power_regs->hw_power_reset); 607 } 608 609 /** 610 * mxs_batt_boot() - Configure the power block to boot from battery input 611 * 612 * This function configures the power block to boot from the battery voltage 613 * supply. 614 */ 615 static void mxs_batt_boot(void) 616 { 617 struct mxs_power_regs *power_regs = 618 (struct mxs_power_regs *)MXS_POWER_BASE; 619 620 clrbits_le32(&power_regs->hw_power_5vctrl, POWER_5VCTRL_PWDN_5VBRNOUT); 621 clrbits_le32(&power_regs->hw_power_5vctrl, POWER_5VCTRL_ENABLE_DCDC); 622 623 clrbits_le32(&power_regs->hw_power_dcdc4p2, 624 POWER_DCDC4P2_ENABLE_DCDC | POWER_DCDC4P2_ENABLE_4P2); 625 writel(POWER_CHARGE_ENABLE_LOAD, &power_regs->hw_power_charge_clr); 626 627 /* 5V to battery handoff. */ 628 setbits_le32(&power_regs->hw_power_5vctrl, POWER_5VCTRL_DCDC_XFER); 629 early_delay(30); 630 clrbits_le32(&power_regs->hw_power_5vctrl, POWER_5VCTRL_DCDC_XFER); 631 632 writel(POWER_CTRL_ENIRQ_DCDC4P2_BO, &power_regs->hw_power_ctrl_clr); 633 634 clrsetbits_le32(&power_regs->hw_power_minpwr, 635 POWER_MINPWR_HALFFETS, POWER_MINPWR_DOUBLE_FETS); 636 637 mxs_power_set_linreg(); 638 639 clrbits_le32(&power_regs->hw_power_vdddctrl, 640 POWER_VDDDCTRL_DISABLE_FET | POWER_VDDDCTRL_ENABLE_LINREG); 641 642 clrbits_le32(&power_regs->hw_power_vddactrl, 643 POWER_VDDACTRL_DISABLE_FET | POWER_VDDACTRL_ENABLE_LINREG); 644 645 clrbits_le32(&power_regs->hw_power_vddioctrl, 646 POWER_VDDIOCTRL_DISABLE_FET); 647 648 setbits_le32(&power_regs->hw_power_5vctrl, 649 POWER_5VCTRL_PWD_CHARGE_4P2_MASK); 650 651 setbits_le32(&power_regs->hw_power_5vctrl, 652 POWER_5VCTRL_ENABLE_DCDC); 653 654 clrsetbits_le32(&power_regs->hw_power_5vctrl, 655 POWER_5VCTRL_CHARGE_4P2_ILIMIT_MASK, 656 0x8 << POWER_5VCTRL_CHARGE_4P2_ILIMIT_OFFSET); 657 } 658 659 /** 660 * mxs_handle_5v_conflict() - Test if the 5V input is reliable 661 * 662 * This function tests if the 5V input can reliably supply the system. If it 663 * can, then proceed to configuring the system to boot from 5V source, otherwise 664 * try booting from battery supply. If we can not boot from battery supply 665 * either, shut down the system. 666 */ 667 static void mxs_handle_5v_conflict(void) 668 { 669 struct mxs_power_regs *power_regs = 670 (struct mxs_power_regs *)MXS_POWER_BASE; 671 uint32_t tmp; 672 673 setbits_le32(&power_regs->hw_power_vddioctrl, 674 POWER_VDDIOCTRL_BO_OFFSET_MASK); 675 676 for (;;) { 677 tmp = readl(&power_regs->hw_power_sts); 678 679 if (tmp & POWER_STS_VDDIO_BO) { 680 /* 681 * VDDIO has a brownout, then the VDD5V_GT_VDDIO becomes 682 * unreliable 683 */ 684 mxs_powerdown(); 685 break; 686 } 687 688 if (tmp & POWER_STS_VDD5V_GT_VDDIO) { 689 mxs_boot_valid_5v(); 690 break; 691 } else { 692 mxs_powerdown(); 693 break; 694 } 695 696 if (tmp & POWER_STS_PSWITCH_MASK) { 697 mxs_batt_boot(); 698 break; 699 } 700 } 701 } 702 703 /** 704 * mxs_5v_boot() - Configure the power block to boot from 5V input 705 * 706 * This function handles configuration of the power block when supplied by 707 * a 5V input. 708 */ 709 static void mxs_5v_boot(void) 710 { 711 struct mxs_power_regs *power_regs = 712 (struct mxs_power_regs *)MXS_POWER_BASE; 713 714 /* 715 * NOTE: In original IMX-Bootlets, this also checks for VBUSVALID, 716 * but their implementation always returns 1 so we omit it here. 717 */ 718 if (readl(&power_regs->hw_power_sts) & POWER_STS_VDD5V_GT_VDDIO) { 719 mxs_boot_valid_5v(); 720 return; 721 } 722 723 early_delay(1000); 724 if (readl(&power_regs->hw_power_sts) & POWER_STS_VDD5V_GT_VDDIO) { 725 mxs_boot_valid_5v(); 726 return; 727 } 728 729 mxs_handle_5v_conflict(); 730 } 731 732 /** 733 * mxs_init_batt_bo() - Configure battery brownout threshold 734 * 735 * This function configures the battery input brownout threshold. The value 736 * at which the battery brownout happens is configured to 3.0V in the code. 737 */ 738 static void mxs_init_batt_bo(void) 739 { 740 struct mxs_power_regs *power_regs = 741 (struct mxs_power_regs *)MXS_POWER_BASE; 742 743 /* Brownout at 3V */ 744 clrsetbits_le32(&power_regs->hw_power_battmonitor, 745 POWER_BATTMONITOR_BRWNOUT_LVL_MASK, 746 15 << POWER_BATTMONITOR_BRWNOUT_LVL_OFFSET); 747 748 writel(POWER_CTRL_BATT_BO_IRQ, &power_regs->hw_power_ctrl_clr); 749 writel(POWER_CTRL_ENIRQ_BATT_BO, &power_regs->hw_power_ctrl_clr); 750 } 751 752 /** 753 * mxs_switch_vddd_to_dcdc_source() - Switch VDDD rail to DC-DC converter 754 * 755 * This function turns off the VDDD linear regulator and therefore makes 756 * the VDDD rail be supplied only by the DC-DC converter. 757 */ 758 static void mxs_switch_vddd_to_dcdc_source(void) 759 { 760 struct mxs_power_regs *power_regs = 761 (struct mxs_power_regs *)MXS_POWER_BASE; 762 763 clrsetbits_le32(&power_regs->hw_power_vdddctrl, 764 POWER_VDDDCTRL_LINREG_OFFSET_MASK, 765 POWER_VDDDCTRL_LINREG_OFFSET_1STEPS_BELOW); 766 767 clrbits_le32(&power_regs->hw_power_vdddctrl, 768 POWER_VDDDCTRL_DISABLE_FET | POWER_VDDDCTRL_ENABLE_LINREG | 769 POWER_VDDDCTRL_DISABLE_STEPPING); 770 } 771 772 /** 773 * mxs_power_configure_power_source() - Configure power block source 774 * 775 * This function is the core of the power configuration logic. The function 776 * selects the power block input source and configures the whole power block 777 * accordingly. After the configuration is complete and the system is stable 778 * again, the function switches the CPU clock source back to PLL. Finally, 779 * the function switches the voltage rails to DC-DC converter. 780 */ 781 static void mxs_power_configure_power_source(void) 782 { 783 int batt_ready, batt_good; 784 struct mxs_power_regs *power_regs = 785 (struct mxs_power_regs *)MXS_POWER_BASE; 786 struct mxs_lradc_regs *lradc_regs = 787 (struct mxs_lradc_regs *)MXS_LRADC_BASE; 788 789 mxs_src_power_init(); 790 791 if (readl(&power_regs->hw_power_sts) & POWER_STS_VDD5V_GT_VDDIO) { 792 batt_ready = mxs_is_batt_ready(); 793 if (batt_ready) { 794 /* 5V source detected, good battery detected. */ 795 mxs_batt_boot(); 796 } else { 797 batt_good = mxs_is_batt_good(); 798 if (!batt_good) { 799 /* 5V source detected, bad battery detected. */ 800 writel(LRADC_CONVERSION_AUTOMATIC, 801 &lradc_regs->hw_lradc_conversion_clr); 802 clrbits_le32(&power_regs->hw_power_battmonitor, 803 POWER_BATTMONITOR_BATT_VAL_MASK); 804 } 805 mxs_5v_boot(); 806 } 807 } else { 808 /* 5V not detected, booting from battery. */ 809 mxs_batt_boot(); 810 } 811 812 mxs_power_clock2pll(); 813 814 mxs_init_batt_bo(); 815 816 mxs_switch_vddd_to_dcdc_source(); 817 818 #ifdef CONFIG_MX23 819 /* Fire up the VDDMEM LinReg now that we're all set. */ 820 writel(POWER_VDDMEMCTRL_ENABLE_LINREG | POWER_VDDMEMCTRL_ENABLE_ILIMIT, 821 &power_regs->hw_power_vddmemctrl); 822 #endif 823 } 824 825 /** 826 * mxs_enable_output_rail_protection() - Enable power rail protection 827 * 828 * This function enables overload protection on the power rails. This is 829 * triggered if the power rails' voltage drops rapidly due to overload and 830 * in such case, the supply to the powerrail is cut-off, protecting the 831 * CPU from damage. Note that under such condition, the system will likely 832 * crash or misbehave. 833 */ 834 static void mxs_enable_output_rail_protection(void) 835 { 836 struct mxs_power_regs *power_regs = 837 (struct mxs_power_regs *)MXS_POWER_BASE; 838 839 writel(POWER_CTRL_VDDD_BO_IRQ | POWER_CTRL_VDDA_BO_IRQ | 840 POWER_CTRL_VDDIO_BO_IRQ, &power_regs->hw_power_ctrl_clr); 841 842 setbits_le32(&power_regs->hw_power_vdddctrl, 843 POWER_VDDDCTRL_PWDN_BRNOUT); 844 845 setbits_le32(&power_regs->hw_power_vddactrl, 846 POWER_VDDACTRL_PWDN_BRNOUT); 847 848 setbits_le32(&power_regs->hw_power_vddioctrl, 849 POWER_VDDIOCTRL_PWDN_BRNOUT); 850 } 851 852 /** 853 * mxs_get_vddio_power_source_off() - Get VDDIO rail power source 854 * 855 * This function tests if the VDDIO rail is supplied by linear regulator 856 * or by the DC-DC converter. Returns 1 if powered by linear regulator, 857 * returns 0 if powered by the DC-DC converter. 858 */ 859 static int mxs_get_vddio_power_source_off(void) 860 { 861 struct mxs_power_regs *power_regs = 862 (struct mxs_power_regs *)MXS_POWER_BASE; 863 uint32_t tmp; 864 865 if (readl(&power_regs->hw_power_sts) & POWER_STS_VDD5V_GT_VDDIO) { 866 tmp = readl(&power_regs->hw_power_vddioctrl); 867 if (tmp & POWER_VDDIOCTRL_DISABLE_FET) { 868 if ((tmp & POWER_VDDIOCTRL_LINREG_OFFSET_MASK) == 869 POWER_VDDIOCTRL_LINREG_OFFSET_0STEPS) { 870 return 1; 871 } 872 } 873 874 if (!(readl(&power_regs->hw_power_5vctrl) & 875 POWER_5VCTRL_ENABLE_DCDC)) { 876 if ((tmp & POWER_VDDIOCTRL_LINREG_OFFSET_MASK) == 877 POWER_VDDIOCTRL_LINREG_OFFSET_0STEPS) { 878 return 1; 879 } 880 } 881 } 882 883 return 0; 884 885 } 886 887 /** 888 * mxs_get_vddd_power_source_off() - Get VDDD rail power source 889 * 890 * This function tests if the VDDD rail is supplied by linear regulator 891 * or by the DC-DC converter. Returns 1 if powered by linear regulator, 892 * returns 0 if powered by the DC-DC converter. 893 */ 894 static int mxs_get_vddd_power_source_off(void) 895 { 896 struct mxs_power_regs *power_regs = 897 (struct mxs_power_regs *)MXS_POWER_BASE; 898 uint32_t tmp; 899 900 tmp = readl(&power_regs->hw_power_vdddctrl); 901 if (tmp & POWER_VDDDCTRL_DISABLE_FET) { 902 if ((tmp & POWER_VDDDCTRL_LINREG_OFFSET_MASK) == 903 POWER_VDDDCTRL_LINREG_OFFSET_0STEPS) { 904 return 1; 905 } 906 } 907 908 if (readl(&power_regs->hw_power_sts) & POWER_STS_VDD5V_GT_VDDIO) { 909 if (!(readl(&power_regs->hw_power_5vctrl) & 910 POWER_5VCTRL_ENABLE_DCDC)) { 911 return 1; 912 } 913 } 914 915 if (!(tmp & POWER_VDDDCTRL_ENABLE_LINREG)) { 916 if ((tmp & POWER_VDDDCTRL_LINREG_OFFSET_MASK) == 917 POWER_VDDDCTRL_LINREG_OFFSET_1STEPS_BELOW) { 918 return 1; 919 } 920 } 921 922 return 0; 923 } 924 925 struct mxs_vddx_cfg { 926 uint32_t *reg; 927 uint8_t step_mV; 928 uint16_t lowest_mV; 929 int (*powered_by_linreg)(void); 930 uint32_t trg_mask; 931 uint32_t bo_irq; 932 uint32_t bo_enirq; 933 uint32_t bo_offset_mask; 934 uint32_t bo_offset_offset; 935 }; 936 937 static const struct mxs_vddx_cfg mxs_vddio_cfg = { 938 .reg = &(((struct mxs_power_regs *)MXS_POWER_BASE)-> 939 hw_power_vddioctrl), 940 #if defined(CONFIG_MX23) 941 .step_mV = 25, 942 #else 943 .step_mV = 50, 944 #endif 945 .lowest_mV = 2800, 946 .powered_by_linreg = mxs_get_vddio_power_source_off, 947 .trg_mask = POWER_VDDIOCTRL_TRG_MASK, 948 .bo_irq = POWER_CTRL_VDDIO_BO_IRQ, 949 .bo_enirq = POWER_CTRL_ENIRQ_VDDIO_BO, 950 .bo_offset_mask = POWER_VDDIOCTRL_BO_OFFSET_MASK, 951 .bo_offset_offset = POWER_VDDIOCTRL_BO_OFFSET_OFFSET, 952 }; 953 954 static const struct mxs_vddx_cfg mxs_vddd_cfg = { 955 .reg = &(((struct mxs_power_regs *)MXS_POWER_BASE)-> 956 hw_power_vdddctrl), 957 .step_mV = 25, 958 .lowest_mV = 800, 959 .powered_by_linreg = mxs_get_vddd_power_source_off, 960 .trg_mask = POWER_VDDDCTRL_TRG_MASK, 961 .bo_irq = POWER_CTRL_VDDD_BO_IRQ, 962 .bo_enirq = POWER_CTRL_ENIRQ_VDDD_BO, 963 .bo_offset_mask = POWER_VDDDCTRL_BO_OFFSET_MASK, 964 .bo_offset_offset = POWER_VDDDCTRL_BO_OFFSET_OFFSET, 965 }; 966 967 #ifdef CONFIG_MX23 968 static const struct mxs_vddx_cfg mxs_vddmem_cfg = { 969 .reg = &(((struct mxs_power_regs *)MXS_POWER_BASE)-> 970 hw_power_vddmemctrl), 971 .step_mV = 50, 972 .lowest_mV = 1700, 973 .powered_by_linreg = NULL, 974 .trg_mask = POWER_VDDMEMCTRL_TRG_MASK, 975 .bo_irq = 0, 976 .bo_enirq = 0, 977 .bo_offset_mask = 0, 978 .bo_offset_offset = 0, 979 }; 980 #endif 981 982 /** 983 * mxs_power_set_vddx() - Configure voltage on DC-DC converter rail 984 * @cfg: Configuration data of the DC-DC converter rail 985 * @new_target: New target voltage of the DC-DC converter rail 986 * @new_brownout: New brownout trigger voltage 987 * 988 * This function configures the output voltage on the DC-DC converter rail. 989 * The rail is selected by the @cfg argument. The new voltage target is 990 * selected by the @new_target and the voltage is specified in mV. The 991 * new brownout value is selected by the @new_brownout argument and the 992 * value is also in mV. 993 */ 994 static void mxs_power_set_vddx(const struct mxs_vddx_cfg *cfg, 995 uint32_t new_target, uint32_t new_brownout) 996 { 997 struct mxs_power_regs *power_regs = 998 (struct mxs_power_regs *)MXS_POWER_BASE; 999 uint32_t cur_target, diff, bo_int = 0; 1000 uint32_t powered_by_linreg = 0; 1001 int adjust_up, tmp; 1002 1003 new_brownout = DIV_ROUND(new_target - new_brownout, cfg->step_mV); 1004 1005 cur_target = readl(cfg->reg); 1006 cur_target &= cfg->trg_mask; 1007 cur_target *= cfg->step_mV; 1008 cur_target += cfg->lowest_mV; 1009 1010 adjust_up = new_target > cur_target; 1011 if (cfg->powered_by_linreg) 1012 powered_by_linreg = cfg->powered_by_linreg(); 1013 1014 if (adjust_up && cfg->bo_irq) { 1015 if (powered_by_linreg) { 1016 bo_int = readl(cfg->reg); 1017 clrbits_le32(cfg->reg, cfg->bo_enirq); 1018 } 1019 setbits_le32(cfg->reg, cfg->bo_offset_mask); 1020 } 1021 1022 do { 1023 if (abs(new_target - cur_target) > 100) { 1024 if (adjust_up) 1025 diff = cur_target + 100; 1026 else 1027 diff = cur_target - 100; 1028 } else { 1029 diff = new_target; 1030 } 1031 1032 diff -= cfg->lowest_mV; 1033 diff /= cfg->step_mV; 1034 1035 clrsetbits_le32(cfg->reg, cfg->trg_mask, diff); 1036 1037 if (powered_by_linreg || 1038 (readl(&power_regs->hw_power_sts) & 1039 POWER_STS_VDD5V_GT_VDDIO)) 1040 early_delay(500); 1041 else { 1042 for (;;) { 1043 tmp = readl(&power_regs->hw_power_sts); 1044 if (tmp & POWER_STS_DC_OK) 1045 break; 1046 } 1047 } 1048 1049 cur_target = readl(cfg->reg); 1050 cur_target &= cfg->trg_mask; 1051 cur_target *= cfg->step_mV; 1052 cur_target += cfg->lowest_mV; 1053 } while (new_target > cur_target); 1054 1055 if (cfg->bo_irq) { 1056 if (adjust_up && powered_by_linreg) { 1057 writel(cfg->bo_irq, &power_regs->hw_power_ctrl_clr); 1058 if (bo_int & cfg->bo_enirq) 1059 setbits_le32(cfg->reg, cfg->bo_enirq); 1060 } 1061 1062 clrsetbits_le32(cfg->reg, cfg->bo_offset_mask, 1063 new_brownout << cfg->bo_offset_offset); 1064 } 1065 } 1066 1067 /** 1068 * mxs_setup_batt_detect() - Start the battery voltage measurement logic 1069 * 1070 * This function starts and configures the LRADC block. This allows the 1071 * power initialization code to measure battery voltage and based on this 1072 * knowledge, decide whether to boot at all, boot from battery or boot 1073 * from 5V input. 1074 */ 1075 static void mxs_setup_batt_detect(void) 1076 { 1077 mxs_lradc_init(); 1078 mxs_lradc_enable_batt_measurement(); 1079 early_delay(10); 1080 } 1081 1082 /** 1083 * mxs_ungate_power() - Ungate the POWER block 1084 * 1085 * This function ungates clock to the power block. In case the power block 1086 * was still gated at this point, it will not be possible to configure the 1087 * block and therefore the power initialization would fail. This function 1088 * is only needed on i.MX233, on i.MX28 the power block is always ungated. 1089 */ 1090 static void mxs_ungate_power(void) 1091 { 1092 #ifdef CONFIG_MX23 1093 struct mxs_power_regs *power_regs = 1094 (struct mxs_power_regs *)MXS_POWER_BASE; 1095 1096 writel(POWER_CTRL_CLKGATE, &power_regs->hw_power_ctrl_clr); 1097 #endif 1098 } 1099 1100 /** 1101 * mxs_power_init() - The power block init main function 1102 * 1103 * This function calls all the power block initialization functions in 1104 * proper sequence to start the power block. 1105 */ 1106 void mxs_power_init(void) 1107 { 1108 struct mxs_power_regs *power_regs = 1109 (struct mxs_power_regs *)MXS_POWER_BASE; 1110 1111 mxs_ungate_power(); 1112 1113 mxs_power_clock2xtal(); 1114 mxs_power_set_auto_restart(); 1115 mxs_power_set_linreg(); 1116 mxs_power_setup_5v_detect(); 1117 1118 mxs_setup_batt_detect(); 1119 1120 mxs_power_configure_power_source(); 1121 mxs_enable_output_rail_protection(); 1122 1123 mxs_power_set_vddx(&mxs_vddio_cfg, 3300, 3150); 1124 mxs_power_set_vddx(&mxs_vddd_cfg, 1500, 1000); 1125 #ifdef CONFIG_MX23 1126 mxs_power_set_vddx(&mxs_vddmem_cfg, 2500, 1700); 1127 #endif 1128 writel(POWER_CTRL_VDDD_BO_IRQ | POWER_CTRL_VDDA_BO_IRQ | 1129 POWER_CTRL_VDDIO_BO_IRQ | POWER_CTRL_VDD5V_DROOP_IRQ | 1130 POWER_CTRL_VBUS_VALID_IRQ | POWER_CTRL_BATT_BO_IRQ | 1131 POWER_CTRL_DCDC4P2_BO_IRQ, &power_regs->hw_power_ctrl_clr); 1132 1133 writel(POWER_5VCTRL_PWDN_5VBRNOUT, &power_regs->hw_power_5vctrl_set); 1134 1135 early_delay(1000); 1136 } 1137 1138 #ifdef CONFIG_SPL_MXS_PSWITCH_WAIT 1139 /** 1140 * mxs_power_wait_pswitch() - Wait for power switch to be pressed 1141 * 1142 * This function waits until the power-switch was pressed to start booting 1143 * the board. 1144 */ 1145 void mxs_power_wait_pswitch(void) 1146 { 1147 struct mxs_power_regs *power_regs = 1148 (struct mxs_power_regs *)MXS_POWER_BASE; 1149 1150 while (!(readl(&power_regs->hw_power_sts) & POWER_STS_PSWITCH_MASK)) 1151 ; 1152 } 1153 #endif 1154