1 /* 2 * Freescale i.MX28 RAM init 3 * 4 * Copyright (C) 2011 Marek Vasut <marek.vasut@gmail.com> 5 * on behalf of DENX Software Engineering GmbH 6 * 7 * SPDX-License-Identifier: GPL-2.0+ 8 */ 9 10 #include <common.h> 11 #include <config.h> 12 #include <asm/io.h> 13 #include <asm/arch/imx-regs.h> 14 #include <asm/arch/sys_proto.h> 15 #include <linux/compiler.h> 16 17 #include "mxs_init.h" 18 19 static uint32_t dram_vals[] = { 20 /* 21 * i.MX28 DDR2 at 200MHz 22 */ 23 #if defined(CONFIG_MX28) 24 0x00000000, 0x00000000, 0x00000000, 0x00000000, 25 0x00000000, 0x00000000, 0x00000000, 0x00000000, 26 0x00000000, 0x00000000, 0x00000000, 0x00000000, 27 0x00000000, 0x00000000, 0x00000000, 0x00000000, 28 0x00000000, 0x00000100, 0x00000000, 0x00000000, 29 0x00000000, 0x00000000, 0x00000000, 0x00000000, 30 0x00000000, 0x00000000, 0x00010101, 0x01010101, 31 0x000f0f01, 0x0f02020a, 0x00000000, 0x00010101, 32 0x00000100, 0x00000100, 0x00000000, 0x00000002, 33 0x01010000, 0x07080403, 0x06005003, 0x0a0000c8, 34 0x02009c40, 0x0002030c, 0x0036a609, 0x031a0612, 35 0x02030202, 0x00c8001c, 0x00000000, 0x00000000, 36 0x00012100, 0xffff0303, 0x00012100, 0xffff0303, 37 0x00012100, 0xffff0303, 0x00012100, 0xffff0303, 38 0x00000003, 0x00000000, 0x00000000, 0x00000000, 39 0x00000000, 0x00000000, 0x00000000, 0x00000000, 40 0x00000000, 0x00000000, 0x00000612, 0x01000F02, 41 0x06120612, 0x00000200, 0x00020007, 0xf4004a27, 42 0xf4004a27, 0xf4004a27, 0xf4004a27, 0x07000300, 43 0x07000300, 0x07400300, 0x07400300, 0x00000005, 44 0x00000000, 0x00000000, 0x01000000, 0x01020408, 45 0x08040201, 0x000f1133, 0x00000000, 0x00001f04, 46 0x00001f04, 0x00001f04, 0x00001f04, 0x00001f04, 47 0x00001f04, 0x00001f04, 0x00001f04, 0x00000000, 48 0x00000000, 0x00000000, 0x00000000, 0x00000000, 49 0x00000000, 0x00000000, 0x00000000, 0x00000000, 50 0x00000000, 0x00000000, 0x00000000, 0x00000000, 51 0x00000000, 0x00000000, 0x00000000, 0x00000000, 52 0x00000000, 0x00000000, 0x00000000, 0x00000000, 53 0x00000000, 0x00000000, 0x00000000, 0x00000000, 54 0x00000000, 0x00000000, 0x00000000, 0x00000000, 55 0x00000000, 0x00000000, 0x00000000, 0x00000000, 56 0x00000000, 0x00000000, 0x00000000, 0x00000000, 57 0x00000000, 0x00000000, 0x00000000, 0x00000000, 58 0x00000000, 0x00000000, 0x00000000, 0x00000000, 59 0x00000000, 0x00000000, 0x00000000, 0x00000000, 60 0x00000000, 0x00000000, 0x00000000, 0x00000000, 61 0x00000000, 0x00000000, 0x00000000, 0x00000000, 62 0x00000000, 0x00000000, 0x00000000, 0x00000000, 63 0x00000000, 0x00000000, 0x00000000, 0x00000000, 64 0x00000000, 0x00000000, 0x00010000, 0x00030404, 65 0x00000003, 0x00000000, 0x00000000, 0x00000000, 66 0x00000000, 0x00000000, 0x00000000, 0x01010000, 67 0x01000000, 0x03030000, 0x00010303, 0x01020202, 68 0x00000000, 0x02040303, 0x21002103, 0x00061200, 69 0x06120612, 0x04420442, 0x04420442, 0x00040004, 70 0x00040004, 0x00000000, 0x00000000, 0x00000000, 71 0x00000000, 0xffffffff 72 73 /* 74 * i.MX23 DDR at 133MHz 75 */ 76 #elif defined(CONFIG_MX23) 77 0x01010001, 0x00010100, 0x01000101, 0x00000001, 78 0x00000101, 0x00000000, 0x00010000, 0x01000001, 79 0x00000000, 0x00000001, 0x07000200, 0x00070202, 80 0x02020000, 0x04040a01, 0x00000201, 0x02040000, 81 0x02000000, 0x19000f08, 0x0d0d0000, 0x02021313, 82 0x02061521, 0x0000000a, 0x00080008, 0x00200020, 83 0x00200020, 0x00200020, 0x000003f7, 0x00000000, 84 0x00000000, 0x00000020, 0x00000020, 0x00c80000, 85 0x000a23cd, 0x000000c8, 0x00006665, 0x00000000, 86 0x00000101, 0x00040001, 0x00000000, 0x00000000, 87 0x00010000 88 #else 89 #error Unsupported memory initialization 90 #endif 91 }; 92 93 __weak void mxs_adjust_memory_params(uint32_t *dram_vals) 94 { 95 debug("SPL: Using default SDRAM parameters\n"); 96 } 97 98 #ifdef CONFIG_MX28 99 static void initialize_dram_values(void) 100 { 101 int i; 102 103 debug("SPL: Setting mx28 board specific SDRAM parameters\n"); 104 mxs_adjust_memory_params(dram_vals); 105 106 debug("SPL: Applying SDRAM parameters\n"); 107 for (i = 0; i < ARRAY_SIZE(dram_vals); i++) 108 writel(dram_vals[i], MXS_DRAM_BASE + (4 * i)); 109 } 110 #else 111 static void initialize_dram_values(void) 112 { 113 int i; 114 115 debug("SPL: Setting mx23 board specific SDRAM parameters\n"); 116 mxs_adjust_memory_params(dram_vals); 117 118 /* 119 * HW_DRAM_CTL27, HW_DRAM_CTL28 and HW_DRAM_CTL35 are not initialized as 120 * per FSL bootlets code. 121 * 122 * mx23 Reference Manual marks HW_DRAM_CTL27 and HW_DRAM_CTL28 as 123 * "reserved". 124 * HW_DRAM_CTL8 is setup as the last element. 125 * So skip the initialization of these HW_DRAM_CTL registers. 126 */ 127 debug("SPL: Applying SDRAM parameters\n"); 128 for (i = 0; i < ARRAY_SIZE(dram_vals); i++) { 129 if (i == 8 || i == 27 || i == 28 || i == 35) 130 continue; 131 writel(dram_vals[i], MXS_DRAM_BASE + (4 * i)); 132 } 133 134 /* 135 * Enable tRAS lockout in HW_DRAM_CTL08 ; it must be the last 136 * element to be set 137 */ 138 writel((1 << 24), MXS_DRAM_BASE + (4 * 8)); 139 } 140 #endif 141 142 static void mxs_mem_init_clock(void) 143 { 144 struct mxs_clkctrl_regs *clkctrl_regs = 145 (struct mxs_clkctrl_regs *)MXS_CLKCTRL_BASE; 146 #if defined(CONFIG_MX23) 147 /* Fractional divider for ref_emi is 33 ; 480 * 18 / 33 = 266MHz */ 148 const unsigned char divider = 33; 149 #elif defined(CONFIG_MX28) 150 /* Fractional divider for ref_emi is 21 ; 480 * 18 / 21 = 411MHz */ 151 const unsigned char divider = 21; 152 #endif 153 154 debug("SPL: Initialising FRAC0\n"); 155 156 /* Gate EMI clock */ 157 writeb(CLKCTRL_FRAC_CLKGATE, 158 &clkctrl_regs->hw_clkctrl_frac0_set[CLKCTRL_FRAC0_EMI]); 159 160 /* Set fractional divider for ref_emi */ 161 writeb(CLKCTRL_FRAC_CLKGATE | (divider & CLKCTRL_FRAC_FRAC_MASK), 162 &clkctrl_regs->hw_clkctrl_frac0[CLKCTRL_FRAC0_EMI]); 163 164 /* Ungate EMI clock */ 165 writeb(CLKCTRL_FRAC_CLKGATE, 166 &clkctrl_regs->hw_clkctrl_frac0_clr[CLKCTRL_FRAC0_EMI]); 167 168 early_delay(11000); 169 170 /* Set EMI clock divider for EMI clock to 411 / 2 = 205MHz */ 171 writel((2 << CLKCTRL_EMI_DIV_EMI_OFFSET) | 172 (1 << CLKCTRL_EMI_DIV_XTAL_OFFSET), 173 &clkctrl_regs->hw_clkctrl_emi); 174 175 /* Unbypass EMI */ 176 writel(CLKCTRL_CLKSEQ_BYPASS_EMI, 177 &clkctrl_regs->hw_clkctrl_clkseq_clr); 178 179 early_delay(10000); 180 debug("SPL: FRAC0 Initialised\n"); 181 } 182 183 static void mxs_mem_setup_cpu_and_hbus(void) 184 { 185 struct mxs_clkctrl_regs *clkctrl_regs = 186 (struct mxs_clkctrl_regs *)MXS_CLKCTRL_BASE; 187 188 debug("SPL: Setting CPU and HBUS clock frequencies\n"); 189 190 /* Set fractional divider for ref_cpu to 480 * 18 / 19 = 454MHz 191 * and ungate CPU clock */ 192 writeb(19 & CLKCTRL_FRAC_FRAC_MASK, 193 (uint8_t *)&clkctrl_regs->hw_clkctrl_frac0[CLKCTRL_FRAC0_CPU]); 194 195 /* Set CPU bypass */ 196 writel(CLKCTRL_CLKSEQ_BYPASS_CPU, 197 &clkctrl_regs->hw_clkctrl_clkseq_set); 198 199 /* HBUS = 151MHz */ 200 writel(CLKCTRL_HBUS_DIV_MASK, &clkctrl_regs->hw_clkctrl_hbus_set); 201 writel(((~3) << CLKCTRL_HBUS_DIV_OFFSET) & CLKCTRL_HBUS_DIV_MASK, 202 &clkctrl_regs->hw_clkctrl_hbus_clr); 203 204 early_delay(10000); 205 206 /* CPU clock divider = 1 */ 207 clrsetbits_le32(&clkctrl_regs->hw_clkctrl_cpu, 208 CLKCTRL_CPU_DIV_CPU_MASK, 1); 209 210 /* Disable CPU bypass */ 211 writel(CLKCTRL_CLKSEQ_BYPASS_CPU, 212 &clkctrl_regs->hw_clkctrl_clkseq_clr); 213 214 early_delay(15000); 215 } 216 217 static void mxs_mem_setup_vdda(void) 218 { 219 struct mxs_power_regs *power_regs = 220 (struct mxs_power_regs *)MXS_POWER_BASE; 221 222 debug("SPL: Configuring VDDA\n"); 223 224 writel((0xc << POWER_VDDACTRL_TRG_OFFSET) | 225 (0x7 << POWER_VDDACTRL_BO_OFFSET_OFFSET) | 226 POWER_VDDACTRL_LINREG_OFFSET_1STEPS_BELOW, 227 &power_regs->hw_power_vddactrl); 228 } 229 230 uint32_t mxs_mem_get_size(void) 231 { 232 uint32_t sz, da; 233 uint32_t *vt = (uint32_t *)0x20; 234 /* The following is "subs pc, r14, #4", used as return from DABT. */ 235 const uint32_t data_abort_memdetect_handler = 0xe25ef004; 236 237 /* Replace the DABT handler. */ 238 da = vt[4]; 239 vt[4] = data_abort_memdetect_handler; 240 241 sz = get_ram_size((long *)PHYS_SDRAM_1, PHYS_SDRAM_1_SIZE); 242 243 /* Restore the old DABT handler. */ 244 vt[4] = da; 245 246 return sz; 247 } 248 249 #ifdef CONFIG_MX23 250 static void mx23_mem_setup_vddmem(void) 251 { 252 struct mxs_power_regs *power_regs = 253 (struct mxs_power_regs *)MXS_POWER_BASE; 254 255 debug("SPL: Setting mx23 VDDMEM\n"); 256 257 /* We must wait before and after disabling the current limiter! */ 258 early_delay(10000); 259 260 clrbits_le32(&power_regs->hw_power_vddmemctrl, 261 POWER_VDDMEMCTRL_ENABLE_ILIMIT); 262 263 early_delay(10000); 264 265 } 266 267 static void mx23_mem_init(void) 268 { 269 debug("SPL: Initialising mx23 SDRAM Controller\n"); 270 271 /* 272 * Reset/ungate the EMI block. This is essential, otherwise the system 273 * suffers from memory instability. This thing is mx23 specific and is 274 * no longer present on mx28. 275 */ 276 mxs_reset_block((struct mxs_register_32 *)MXS_EMI_BASE); 277 278 mx23_mem_setup_vddmem(); 279 280 /* 281 * Configure the DRAM registers 282 */ 283 284 /* Clear START and SREFRESH bit from DRAM_CTL8 */ 285 clrbits_le32(MXS_DRAM_BASE + 0x20, (1 << 16) | (1 << 8)); 286 287 initialize_dram_values(); 288 289 /* Set START bit in DRAM_CTL8 */ 290 setbits_le32(MXS_DRAM_BASE + 0x20, 1 << 16); 291 292 clrbits_le32(MXS_DRAM_BASE + 0x40, 1 << 17); 293 294 /* Wait for EMI_STAT bit DRAM_HALTED */ 295 for (;;) { 296 if (!(readl(MXS_EMI_BASE + 0x10) & (1 << 1))) 297 break; 298 early_delay(1000); 299 } 300 301 /* Adjust EMI port priority. */ 302 clrsetbits_le32(0x80020000, 0x1f << 16, 0x2); 303 early_delay(20000); 304 305 setbits_le32(MXS_DRAM_BASE + 0x40, 1 << 19); 306 setbits_le32(MXS_DRAM_BASE + 0x40, 1 << 11); 307 } 308 #endif 309 310 #ifdef CONFIG_MX28 311 static void mx28_mem_init(void) 312 { 313 struct mxs_pinctrl_regs *pinctrl_regs = 314 (struct mxs_pinctrl_regs *)MXS_PINCTRL_BASE; 315 316 debug("SPL: Initialising mx28 SDRAM Controller\n"); 317 318 /* Set DDR2 mode */ 319 writel(PINCTRL_EMI_DS_CTRL_DDR_MODE_DDR2, 320 &pinctrl_regs->hw_pinctrl_emi_ds_ctrl_set); 321 322 /* 323 * Configure the DRAM registers 324 */ 325 326 /* Clear START bit from DRAM_CTL16 */ 327 clrbits_le32(MXS_DRAM_BASE + 0x40, 1); 328 329 initialize_dram_values(); 330 331 /* Clear SREFRESH bit from DRAM_CTL17 */ 332 clrbits_le32(MXS_DRAM_BASE + 0x44, 1); 333 334 /* Set START bit in DRAM_CTL16 */ 335 setbits_le32(MXS_DRAM_BASE + 0x40, 1); 336 337 /* Wait for bit 20 (DRAM init complete) in DRAM_CTL58 */ 338 while (!(readl(MXS_DRAM_BASE + 0xe8) & (1 << 20))) 339 ; 340 } 341 #endif 342 343 void mxs_mem_init(void) 344 { 345 early_delay(11000); 346 347 mxs_mem_init_clock(); 348 349 mxs_mem_setup_vdda(); 350 351 #if defined(CONFIG_MX23) 352 mx23_mem_init(); 353 #elif defined(CONFIG_MX28) 354 mx28_mem_init(); 355 #endif 356 357 early_delay(10000); 358 359 mxs_mem_setup_cpu_and_hbus(); 360 } 361