1 /* 2 * Freescale i.MX28 RAM init 3 * 4 * Copyright (C) 2011 Marek Vasut <marek.vasut@gmail.com> 5 * on behalf of DENX Software Engineering GmbH 6 * 7 * See file CREDITS for list of people who contributed to this 8 * project. 9 * 10 * This program is free software; you can redistribute it and/or 11 * modify it under the terms of the GNU General Public License as 12 * published by the Free Software Foundation; either version 2 of 13 * the License, or (at your option) any later version. 14 * 15 * This program is distributed in the hope that it will be useful, 16 * but WITHOUT ANY WARRANTY; without even the implied warranty of 17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 18 * GNU General Public License for more details. 19 * 20 * You should have received a copy of the GNU General Public License 21 * along with this program; if not, write to the Free Software 22 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 23 * MA 02111-1307 USA 24 */ 25 26 #include <common.h> 27 #include <config.h> 28 #include <asm/io.h> 29 #include <asm/arch/imx-regs.h> 30 31 #include "mxs_init.h" 32 33 static uint32_t mx28_dram_vals[] = { 34 0x00000000, 0x00000000, 0x00000000, 0x00000000, 35 0x00000000, 0x00000000, 0x00000000, 0x00000000, 36 0x00000000, 0x00000000, 0x00000000, 0x00000000, 37 0x00000000, 0x00000000, 0x00000000, 0x00000000, 38 0x00000000, 0x00000100, 0x00000000, 0x00000000, 39 0x00000000, 0x00000000, 0x00000000, 0x00000000, 40 0x00000000, 0x00000000, 0x00010101, 0x01010101, 41 0x000f0f01, 0x0f02020a, 0x00000000, 0x00010101, 42 0x00000100, 0x00000100, 0x00000000, 0x00000002, 43 0x01010000, 0x05060302, 0x06005003, 0x0a0000c8, 44 0x02009c40, 0x0000030c, 0x0036a609, 0x031a0612, 45 0x02030202, 0x00c8001c, 0x00000000, 0x00000000, 46 0x00012100, 0xffff0303, 0x00012100, 0xffff0303, 47 0x00012100, 0xffff0303, 0x00012100, 0xffff0303, 48 0x00000003, 0x00000000, 0x00000000, 0x00000000, 49 0x00000000, 0x00000000, 0x00000000, 0x00000000, 50 0x00000000, 0x00000000, 0x00000612, 0x01000F02, 51 0x06120612, 0x00000200, 0x00020007, 0xf5014b27, 52 0xf5014b27, 0xf5014b27, 0xf5014b27, 0x07000300, 53 0x07000300, 0x07000300, 0x07000300, 0x00000006, 54 0x00000000, 0x00000000, 0x01000000, 0x01020408, 55 0x08040201, 0x000f1133, 0x00000000, 0x00001f04, 56 0x00001f04, 0x00001f04, 0x00001f04, 0x00001f04, 57 0x00001f04, 0x00001f04, 0x00001f04, 0x00000000, 58 0x00000000, 0x00000000, 0x00000000, 0x00000000, 59 0x00000000, 0x00000000, 0x00000000, 0x00000000, 60 0x00000000, 0x00000000, 0x00000000, 0x00000000, 61 0x00000000, 0x00000000, 0x00000000, 0x00000000, 62 0x00000000, 0x00000000, 0x00000000, 0x00000000, 63 0x00000000, 0x00000000, 0x00000000, 0x00000000, 64 0x00000000, 0x00000000, 0x00000000, 0x00000000, 65 0x00000000, 0x00000000, 0x00000000, 0x00000000, 66 0x00000000, 0x00000000, 0x00000000, 0x00000000, 67 0x00000000, 0x00000000, 0x00000000, 0x00000000, 68 0x00000000, 0x00000000, 0x00000000, 0x00000000, 69 0x00000000, 0x00000000, 0x00000000, 0x00000000, 70 0x00000000, 0x00000000, 0x00000000, 0x00000000, 71 0x00000000, 0x00000000, 0x00000000, 0x00000000, 72 0x00000000, 0x00000000, 0x00000000, 0x00000000, 73 0x00000000, 0x00000000, 0x00000000, 0x00000000, 74 0x00000000, 0x00000000, 0x00010000, 0x00020304, 75 0x00000004, 0x00000000, 0x00000000, 0x00000000, 76 0x00000000, 0x00000000, 0x00000000, 0x01010000, 77 0x01000000, 0x03030000, 0x00010303, 0x01020202, 78 0x00000000, 0x02040303, 0x21002103, 0x00061200, 79 0x06120612, 0x04320432, 0x04320432, 0x00040004, 80 0x00040004, 0x00000000, 0x00000000, 0x00000000, 81 0x00000000, 0x00010001 82 }; 83 84 void __mxs_adjust_memory_params(uint32_t *dram_vals) 85 { 86 } 87 void mxs_adjust_memory_params(uint32_t *dram_vals) 88 __attribute__((weak, alias("__mxs_adjust_memory_params"))); 89 90 void init_mx28_200mhz_ddr2(void) 91 { 92 int i; 93 94 mxs_adjust_memory_params(mx28_dram_vals); 95 96 for (i = 0; i < ARRAY_SIZE(mx28_dram_vals); i++) 97 writel(mx28_dram_vals[i], MXS_DRAM_BASE + (4 * i)); 98 } 99 100 void mxs_mem_init_clock(void) 101 { 102 struct mxs_clkctrl_regs *clkctrl_regs = 103 (struct mxs_clkctrl_regs *)MXS_CLKCTRL_BASE; 104 105 /* Gate EMI clock */ 106 writeb(CLKCTRL_FRAC_CLKGATE, 107 &clkctrl_regs->hw_clkctrl_frac0_set[CLKCTRL_FRAC0_EMI]); 108 109 /* Set fractional divider for ref_emi to 480 * 18 / 21 = 411MHz */ 110 writeb(CLKCTRL_FRAC_CLKGATE | (21 & CLKCTRL_FRAC_FRAC_MASK), 111 &clkctrl_regs->hw_clkctrl_frac0[CLKCTRL_FRAC0_EMI]); 112 113 /* Ungate EMI clock */ 114 writeb(CLKCTRL_FRAC_CLKGATE, 115 &clkctrl_regs->hw_clkctrl_frac0_clr[CLKCTRL_FRAC0_EMI]); 116 117 early_delay(11000); 118 119 /* Set EMI clock divider for EMI clock to 411 / 2 = 205MHz */ 120 writel((2 << CLKCTRL_EMI_DIV_EMI_OFFSET) | 121 (1 << CLKCTRL_EMI_DIV_XTAL_OFFSET), 122 &clkctrl_regs->hw_clkctrl_emi); 123 124 /* Unbypass EMI */ 125 writel(CLKCTRL_CLKSEQ_BYPASS_EMI, 126 &clkctrl_regs->hw_clkctrl_clkseq_clr); 127 128 early_delay(10000); 129 } 130 131 void mxs_mem_setup_cpu_and_hbus(void) 132 { 133 struct mxs_clkctrl_regs *clkctrl_regs = 134 (struct mxs_clkctrl_regs *)MXS_CLKCTRL_BASE; 135 136 /* Set fractional divider for ref_cpu to 480 * 18 / 19 = 454MHz 137 * and ungate CPU clock */ 138 writeb(19 & CLKCTRL_FRAC_FRAC_MASK, 139 (uint8_t *)&clkctrl_regs->hw_clkctrl_frac0[CLKCTRL_FRAC0_CPU]); 140 141 /* Set CPU bypass */ 142 writel(CLKCTRL_CLKSEQ_BYPASS_CPU, 143 &clkctrl_regs->hw_clkctrl_clkseq_set); 144 145 /* HBUS = 151MHz */ 146 writel(CLKCTRL_HBUS_DIV_MASK, &clkctrl_regs->hw_clkctrl_hbus_set); 147 writel(((~3) << CLKCTRL_HBUS_DIV_OFFSET) & CLKCTRL_HBUS_DIV_MASK, 148 &clkctrl_regs->hw_clkctrl_hbus_clr); 149 150 early_delay(10000); 151 152 /* CPU clock divider = 1 */ 153 clrsetbits_le32(&clkctrl_regs->hw_clkctrl_cpu, 154 CLKCTRL_CPU_DIV_CPU_MASK, 1); 155 156 /* Disable CPU bypass */ 157 writel(CLKCTRL_CLKSEQ_BYPASS_CPU, 158 &clkctrl_regs->hw_clkctrl_clkseq_clr); 159 160 early_delay(15000); 161 } 162 163 void mxs_mem_setup_vdda(void) 164 { 165 struct mxs_power_regs *power_regs = 166 (struct mxs_power_regs *)MXS_POWER_BASE; 167 168 writel((0xc << POWER_VDDACTRL_TRG_OFFSET) | 169 (0x7 << POWER_VDDACTRL_BO_OFFSET_OFFSET) | 170 POWER_VDDACTRL_LINREG_OFFSET_1STEPS_BELOW, 171 &power_regs->hw_power_vddactrl); 172 } 173 174 void mxs_mem_setup_vddd(void) 175 { 176 struct mxs_power_regs *power_regs = 177 (struct mxs_power_regs *)MXS_POWER_BASE; 178 179 writel((0x1c << POWER_VDDDCTRL_TRG_OFFSET) | 180 (0x7 << POWER_VDDDCTRL_BO_OFFSET_OFFSET) | 181 POWER_VDDDCTRL_LINREG_OFFSET_1STEPS_BELOW, 182 &power_regs->hw_power_vdddctrl); 183 } 184 185 uint32_t mxs_mem_get_size(void) 186 { 187 uint32_t sz, da; 188 uint32_t *vt = (uint32_t *)0x20; 189 /* The following is "subs pc, r14, #4", used as return from DABT. */ 190 const uint32_t data_abort_memdetect_handler = 0xe25ef004; 191 192 /* Replace the DABT handler. */ 193 da = vt[4]; 194 vt[4] = data_abort_memdetect_handler; 195 196 sz = get_ram_size((long *)PHYS_SDRAM_1, PHYS_SDRAM_1_SIZE); 197 198 /* Restore the old DABT handler. */ 199 vt[4] = da; 200 201 return sz; 202 } 203 204 void mxs_mem_init(void) 205 { 206 struct mxs_clkctrl_regs *clkctrl_regs = 207 (struct mxs_clkctrl_regs *)MXS_CLKCTRL_BASE; 208 struct mxs_pinctrl_regs *pinctrl_regs = 209 (struct mxs_pinctrl_regs *)MXS_PINCTRL_BASE; 210 211 /* Set DDR2 mode */ 212 writel(PINCTRL_EMI_DS_CTRL_DDR_MODE_DDR2, 213 &pinctrl_regs->hw_pinctrl_emi_ds_ctrl_set); 214 215 /* Power up PLL0 */ 216 writel(CLKCTRL_PLL0CTRL0_POWER, 217 &clkctrl_regs->hw_clkctrl_pll0ctrl0_set); 218 219 early_delay(11000); 220 221 mxs_mem_init_clock(); 222 223 mxs_mem_setup_vdda(); 224 225 /* 226 * Configure the DRAM registers 227 */ 228 229 /* Clear START bit from DRAM_CTL16 */ 230 clrbits_le32(MXS_DRAM_BASE + 0x40, 1); 231 232 init_mx28_200mhz_ddr2(); 233 234 /* Clear SREFRESH bit from DRAM_CTL17 */ 235 clrbits_le32(MXS_DRAM_BASE + 0x44, 1); 236 237 /* Set START bit in DRAM_CTL16 */ 238 setbits_le32(MXS_DRAM_BASE + 0x40, 1); 239 240 /* Wait for bit 20 (DRAM init complete) in DRAM_CTL58 */ 241 while (!(readl(MXS_DRAM_BASE + 0xe8) & (1 << 20))) 242 ; 243 244 mxs_mem_setup_vddd(); 245 246 early_delay(10000); 247 248 mxs_mem_setup_cpu_and_hbus(); 249 } 250