1 /* 2 * Freescale i.MX28 RAM init 3 * 4 * Copyright (C) 2011 Marek Vasut <marek.vasut@gmail.com> 5 * on behalf of DENX Software Engineering GmbH 6 * 7 * See file CREDITS for list of people who contributed to this 8 * project. 9 * 10 * This program is free software; you can redistribute it and/or 11 * modify it under the terms of the GNU General Public License as 12 * published by the Free Software Foundation; either version 2 of 13 * the License, or (at your option) any later version. 14 * 15 * This program is distributed in the hope that it will be useful, 16 * but WITHOUT ANY WARRANTY; without even the implied warranty of 17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 18 * GNU General Public License for more details. 19 * 20 * You should have received a copy of the GNU General Public License 21 * along with this program; if not, write to the Free Software 22 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 23 * MA 02111-1307 USA 24 */ 25 26 #include <common.h> 27 #include <config.h> 28 #include <asm/io.h> 29 #include <asm/arch/imx-regs.h> 30 #include <asm/arch/sys_proto.h> 31 #include <linux/compiler.h> 32 33 #include "mxs_init.h" 34 35 static uint32_t dram_vals[] = { 36 /* 37 * i.MX28 DDR2 at 200MHz 38 */ 39 #if defined(CONFIG_MX28) 40 0x00000000, 0x00000000, 0x00000000, 0x00000000, 41 0x00000000, 0x00000000, 0x00000000, 0x00000000, 42 0x00000000, 0x00000000, 0x00000000, 0x00000000, 43 0x00000000, 0x00000000, 0x00000000, 0x00000000, 44 0x00000000, 0x00000100, 0x00000000, 0x00000000, 45 0x00000000, 0x00000000, 0x00000000, 0x00000000, 46 0x00000000, 0x00000000, 0x00010101, 0x01010101, 47 0x000f0f01, 0x0f02020a, 0x00000000, 0x00010101, 48 0x00000100, 0x00000100, 0x00000000, 0x00000002, 49 0x01010000, 0x07080403, 0x06005003, 0x0a0000c8, 50 0x02009c40, 0x0002030c, 0x0036a609, 0x031a0612, 51 0x02030202, 0x00c8001c, 0x00000000, 0x00000000, 52 0x00012100, 0xffff0303, 0x00012100, 0xffff0303, 53 0x00012100, 0xffff0303, 0x00012100, 0xffff0303, 54 0x00000003, 0x00000000, 0x00000000, 0x00000000, 55 0x00000000, 0x00000000, 0x00000000, 0x00000000, 56 0x00000000, 0x00000000, 0x00000612, 0x01000F02, 57 0x06120612, 0x00000200, 0x00020007, 0xf4004a27, 58 0xf4004a27, 0xf4004a27, 0xf4004a27, 0x07000300, 59 0x07000300, 0x07400300, 0x07400300, 0x00000005, 60 0x00000000, 0x00000000, 0x01000000, 0x01020408, 61 0x08040201, 0x000f1133, 0x00000000, 0x00001f04, 62 0x00001f04, 0x00001f04, 0x00001f04, 0x00001f04, 63 0x00001f04, 0x00001f04, 0x00001f04, 0x00000000, 64 0x00000000, 0x00000000, 0x00000000, 0x00000000, 65 0x00000000, 0x00000000, 0x00000000, 0x00000000, 66 0x00000000, 0x00000000, 0x00000000, 0x00000000, 67 0x00000000, 0x00000000, 0x00000000, 0x00000000, 68 0x00000000, 0x00000000, 0x00000000, 0x00000000, 69 0x00000000, 0x00000000, 0x00000000, 0x00000000, 70 0x00000000, 0x00000000, 0x00000000, 0x00000000, 71 0x00000000, 0x00000000, 0x00000000, 0x00000000, 72 0x00000000, 0x00000000, 0x00000000, 0x00000000, 73 0x00000000, 0x00000000, 0x00000000, 0x00000000, 74 0x00000000, 0x00000000, 0x00000000, 0x00000000, 75 0x00000000, 0x00000000, 0x00000000, 0x00000000, 76 0x00000000, 0x00000000, 0x00000000, 0x00000000, 77 0x00000000, 0x00000000, 0x00000000, 0x00000000, 78 0x00000000, 0x00000000, 0x00000000, 0x00000000, 79 0x00000000, 0x00000000, 0x00000000, 0x00000000, 80 0x00000000, 0x00000000, 0x00010000, 0x00030404, 81 0x00000003, 0x00000000, 0x00000000, 0x00000000, 82 0x00000000, 0x00000000, 0x00000000, 0x01010000, 83 0x01000000, 0x03030000, 0x00010303, 0x01020202, 84 0x00000000, 0x02040303, 0x21002103, 0x00061200, 85 0x06120612, 0x04420442, 0x04420442, 0x00040004, 86 0x00040004, 0x00000000, 0x00000000, 0x00000000, 87 0x00000000, 0xffffffff 88 89 /* 90 * i.MX23 DDR at 133MHz 91 */ 92 #elif defined(CONFIG_MX23) 93 0x01010001, 0x00010100, 0x01000101, 0x00000001, 94 0x00000101, 0x00000000, 0x00010000, 0x01000001, 95 0x00000000, 0x00000001, 0x07000200, 0x00070202, 96 0x02020000, 0x04040a01, 0x00000201, 0x02040000, 97 0x02000000, 0x19000f08, 0x0d0d0000, 0x02021313, 98 0x02061521, 0x0000000a, 0x00080008, 0x00200020, 99 0x00200020, 0x00200020, 0x000003f7, 0x00000000, 100 0x00000000, 0x00000020, 0x00000020, 0x00c80000, 101 0x000a23cd, 0x000000c8, 0x00006665, 0x00000000, 102 0x00000101, 0x00040001, 0x00000000, 0x00000000, 103 0x00010000 104 #else 105 #error Unsupported memory initialization 106 #endif 107 }; 108 109 __weak void mxs_adjust_memory_params(uint32_t *dram_vals) 110 { 111 } 112 113 #ifdef CONFIG_MX28 114 static void initialize_dram_values(void) 115 { 116 int i; 117 118 mxs_adjust_memory_params(dram_vals); 119 120 for (i = 0; i < ARRAY_SIZE(dram_vals); i++) 121 writel(dram_vals[i], MXS_DRAM_BASE + (4 * i)); 122 } 123 #else 124 static void initialize_dram_values(void) 125 { 126 int i; 127 128 mxs_adjust_memory_params(dram_vals); 129 130 /* 131 * HW_DRAM_CTL27, HW_DRAM_CTL28 and HW_DRAM_CTL35 are not initialized as 132 * per FSL bootlets code. 133 * 134 * mx23 Reference Manual marks HW_DRAM_CTL27 and HW_DRAM_CTL28 as 135 * "reserved". 136 * HW_DRAM_CTL8 is setup as the last element. 137 * So skip the initialization of these HW_DRAM_CTL registers. 138 */ 139 for (i = 0; i < ARRAY_SIZE(dram_vals); i++) { 140 if (i == 8 || i == 27 || i == 28 || i == 35) 141 continue; 142 writel(dram_vals[i], MXS_DRAM_BASE + (4 * i)); 143 } 144 145 /* 146 * Enable tRAS lockout in HW_DRAM_CTL08 ; it must be the last 147 * element to be set 148 */ 149 writel((1 << 24), MXS_DRAM_BASE + (4 * 8)); 150 } 151 #endif 152 153 static void mxs_mem_init_clock(void) 154 { 155 struct mxs_clkctrl_regs *clkctrl_regs = 156 (struct mxs_clkctrl_regs *)MXS_CLKCTRL_BASE; 157 #if defined(CONFIG_MX23) 158 /* Fractional divider for ref_emi is 33 ; 480 * 18 / 33 = 266MHz */ 159 const unsigned char divider = 33; 160 #elif defined(CONFIG_MX28) 161 /* Fractional divider for ref_emi is 21 ; 480 * 18 / 21 = 411MHz */ 162 const unsigned char divider = 21; 163 #endif 164 165 /* Gate EMI clock */ 166 writeb(CLKCTRL_FRAC_CLKGATE, 167 &clkctrl_regs->hw_clkctrl_frac0_set[CLKCTRL_FRAC0_EMI]); 168 169 /* Set fractional divider for ref_emi */ 170 writeb(CLKCTRL_FRAC_CLKGATE | (divider & CLKCTRL_FRAC_FRAC_MASK), 171 &clkctrl_regs->hw_clkctrl_frac0[CLKCTRL_FRAC0_EMI]); 172 173 /* Ungate EMI clock */ 174 writeb(CLKCTRL_FRAC_CLKGATE, 175 &clkctrl_regs->hw_clkctrl_frac0_clr[CLKCTRL_FRAC0_EMI]); 176 177 early_delay(11000); 178 179 /* Set EMI clock divider for EMI clock to 411 / 2 = 205MHz */ 180 writel((2 << CLKCTRL_EMI_DIV_EMI_OFFSET) | 181 (1 << CLKCTRL_EMI_DIV_XTAL_OFFSET), 182 &clkctrl_regs->hw_clkctrl_emi); 183 184 /* Unbypass EMI */ 185 writel(CLKCTRL_CLKSEQ_BYPASS_EMI, 186 &clkctrl_regs->hw_clkctrl_clkseq_clr); 187 188 early_delay(10000); 189 } 190 191 static void mxs_mem_setup_cpu_and_hbus(void) 192 { 193 struct mxs_clkctrl_regs *clkctrl_regs = 194 (struct mxs_clkctrl_regs *)MXS_CLKCTRL_BASE; 195 196 /* Set fractional divider for ref_cpu to 480 * 18 / 19 = 454MHz 197 * and ungate CPU clock */ 198 writeb(19 & CLKCTRL_FRAC_FRAC_MASK, 199 (uint8_t *)&clkctrl_regs->hw_clkctrl_frac0[CLKCTRL_FRAC0_CPU]); 200 201 /* Set CPU bypass */ 202 writel(CLKCTRL_CLKSEQ_BYPASS_CPU, 203 &clkctrl_regs->hw_clkctrl_clkseq_set); 204 205 /* HBUS = 151MHz */ 206 writel(CLKCTRL_HBUS_DIV_MASK, &clkctrl_regs->hw_clkctrl_hbus_set); 207 writel(((~3) << CLKCTRL_HBUS_DIV_OFFSET) & CLKCTRL_HBUS_DIV_MASK, 208 &clkctrl_regs->hw_clkctrl_hbus_clr); 209 210 early_delay(10000); 211 212 /* CPU clock divider = 1 */ 213 clrsetbits_le32(&clkctrl_regs->hw_clkctrl_cpu, 214 CLKCTRL_CPU_DIV_CPU_MASK, 1); 215 216 /* Disable CPU bypass */ 217 writel(CLKCTRL_CLKSEQ_BYPASS_CPU, 218 &clkctrl_regs->hw_clkctrl_clkseq_clr); 219 220 early_delay(15000); 221 } 222 223 static void mxs_mem_setup_vdda(void) 224 { 225 struct mxs_power_regs *power_regs = 226 (struct mxs_power_regs *)MXS_POWER_BASE; 227 228 writel((0xc << POWER_VDDACTRL_TRG_OFFSET) | 229 (0x7 << POWER_VDDACTRL_BO_OFFSET_OFFSET) | 230 POWER_VDDACTRL_LINREG_OFFSET_1STEPS_BELOW, 231 &power_regs->hw_power_vddactrl); 232 } 233 234 uint32_t mxs_mem_get_size(void) 235 { 236 uint32_t sz, da; 237 uint32_t *vt = (uint32_t *)0x20; 238 /* The following is "subs pc, r14, #4", used as return from DABT. */ 239 const uint32_t data_abort_memdetect_handler = 0xe25ef004; 240 241 /* Replace the DABT handler. */ 242 da = vt[4]; 243 vt[4] = data_abort_memdetect_handler; 244 245 sz = get_ram_size((long *)PHYS_SDRAM_1, PHYS_SDRAM_1_SIZE); 246 247 /* Restore the old DABT handler. */ 248 vt[4] = da; 249 250 return sz; 251 } 252 253 #ifdef CONFIG_MX23 254 static void mx23_mem_setup_vddmem(void) 255 { 256 struct mxs_power_regs *power_regs = 257 (struct mxs_power_regs *)MXS_POWER_BASE; 258 259 clrbits_le32(&power_regs->hw_power_vddmemctrl, 260 POWER_VDDMEMCTRL_ENABLE_ILIMIT); 261 262 } 263 264 static void mx23_mem_init(void) 265 { 266 /* 267 * Reset/ungate the EMI block. This is essential, otherwise the system 268 * suffers from memory instability. This thing is mx23 specific and is 269 * no longer present on mx28. 270 */ 271 mxs_reset_block((struct mxs_register_32 *)MXS_EMI_BASE); 272 273 mx23_mem_setup_vddmem(); 274 275 /* 276 * Configure the DRAM registers 277 */ 278 279 /* Clear START and SREFRESH bit from DRAM_CTL8 */ 280 clrbits_le32(MXS_DRAM_BASE + 0x20, (1 << 16) | (1 << 8)); 281 282 initialize_dram_values(); 283 284 /* Set START bit in DRAM_CTL8 */ 285 setbits_le32(MXS_DRAM_BASE + 0x20, 1 << 16); 286 287 clrbits_le32(MXS_DRAM_BASE + 0x40, 1 << 17); 288 early_delay(20000); 289 290 /* Adjust EMI port priority. */ 291 clrsetbits_le32(0x80020000, 0x1f << 16, 0x2); 292 early_delay(20000); 293 294 setbits_le32(MXS_DRAM_BASE + 0x40, 1 << 19); 295 setbits_le32(MXS_DRAM_BASE + 0x40, 1 << 11); 296 } 297 #endif 298 299 #ifdef CONFIG_MX28 300 static void mx28_mem_init(void) 301 { 302 struct mxs_pinctrl_regs *pinctrl_regs = 303 (struct mxs_pinctrl_regs *)MXS_PINCTRL_BASE; 304 305 /* Set DDR2 mode */ 306 writel(PINCTRL_EMI_DS_CTRL_DDR_MODE_DDR2, 307 &pinctrl_regs->hw_pinctrl_emi_ds_ctrl_set); 308 309 /* 310 * Configure the DRAM registers 311 */ 312 313 /* Clear START bit from DRAM_CTL16 */ 314 clrbits_le32(MXS_DRAM_BASE + 0x40, 1); 315 316 initialize_dram_values(); 317 318 /* Clear SREFRESH bit from DRAM_CTL17 */ 319 clrbits_le32(MXS_DRAM_BASE + 0x44, 1); 320 321 /* Set START bit in DRAM_CTL16 */ 322 setbits_le32(MXS_DRAM_BASE + 0x40, 1); 323 324 /* Wait for bit 20 (DRAM init complete) in DRAM_CTL58 */ 325 while (!(readl(MXS_DRAM_BASE + 0xe8) & (1 << 20))) 326 ; 327 } 328 #endif 329 330 void mxs_mem_init(void) 331 { 332 early_delay(11000); 333 334 mxs_mem_init_clock(); 335 336 mxs_mem_setup_vdda(); 337 338 #if defined(CONFIG_MX23) 339 mx23_mem_init(); 340 #elif defined(CONFIG_MX28) 341 mx28_mem_init(); 342 #endif 343 344 early_delay(10000); 345 346 mxs_mem_setup_cpu_and_hbus(); 347 } 348