1 /* 2 * Freescale i.MX28 RAM init 3 * 4 * Copyright (C) 2011 Marek Vasut <marek.vasut@gmail.com> 5 * on behalf of DENX Software Engineering GmbH 6 * 7 * See file CREDITS for list of people who contributed to this 8 * project. 9 * 10 * This program is free software; you can redistribute it and/or 11 * modify it under the terms of the GNU General Public License as 12 * published by the Free Software Foundation; either version 2 of 13 * the License, or (at your option) any later version. 14 * 15 * This program is distributed in the hope that it will be useful, 16 * but WITHOUT ANY WARRANTY; without even the implied warranty of 17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 18 * GNU General Public License for more details. 19 * 20 * You should have received a copy of the GNU General Public License 21 * along with this program; if not, write to the Free Software 22 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 23 * MA 02111-1307 USA 24 */ 25 26 #include <common.h> 27 #include <config.h> 28 #include <asm/io.h> 29 #include <asm/arch/imx-regs.h> 30 #include <linux/compiler.h> 31 32 #include "mxs_init.h" 33 34 static uint32_t dram_vals[] = { 35 /* 36 * i.MX28 DDR2 at 200MHz 37 */ 38 #if defined(CONFIG_MX28) 39 0x00000000, 0x00000000, 0x00000000, 0x00000000, 40 0x00000000, 0x00000000, 0x00000000, 0x00000000, 41 0x00000000, 0x00000000, 0x00000000, 0x00000000, 42 0x00000000, 0x00000000, 0x00000000, 0x00000000, 43 0x00000000, 0x00000100, 0x00000000, 0x00000000, 44 0x00000000, 0x00000000, 0x00000000, 0x00000000, 45 0x00000000, 0x00000000, 0x00010101, 0x01010101, 46 0x000f0f01, 0x0f02020a, 0x00000000, 0x00010101, 47 0x00000100, 0x00000100, 0x00000000, 0x00000002, 48 0x01010000, 0x05060302, 0x06005003, 0x0a0000c8, 49 0x02009c40, 0x0000030c, 0x0036a609, 0x031a0612, 50 0x02030202, 0x00c8001c, 0x00000000, 0x00000000, 51 0x00012100, 0xffff0303, 0x00012100, 0xffff0303, 52 0x00012100, 0xffff0303, 0x00012100, 0xffff0303, 53 0x00000003, 0x00000000, 0x00000000, 0x00000000, 54 0x00000000, 0x00000000, 0x00000000, 0x00000000, 55 0x00000000, 0x00000000, 0x00000612, 0x01000F02, 56 0x06120612, 0x00000200, 0x00020007, 0xf5014b27, 57 0xf5014b27, 0xf5014b27, 0xf5014b27, 0x07000300, 58 0x07000300, 0x07000300, 0x07000300, 0x00000006, 59 0x00000000, 0x00000000, 0x01000000, 0x01020408, 60 0x08040201, 0x000f1133, 0x00000000, 0x00001f04, 61 0x00001f04, 0x00001f04, 0x00001f04, 0x00001f04, 62 0x00001f04, 0x00001f04, 0x00001f04, 0x00000000, 63 0x00000000, 0x00000000, 0x00000000, 0x00000000, 64 0x00000000, 0x00000000, 0x00000000, 0x00000000, 65 0x00000000, 0x00000000, 0x00000000, 0x00000000, 66 0x00000000, 0x00000000, 0x00000000, 0x00000000, 67 0x00000000, 0x00000000, 0x00000000, 0x00000000, 68 0x00000000, 0x00000000, 0x00000000, 0x00000000, 69 0x00000000, 0x00000000, 0x00000000, 0x00000000, 70 0x00000000, 0x00000000, 0x00000000, 0x00000000, 71 0x00000000, 0x00000000, 0x00000000, 0x00000000, 72 0x00000000, 0x00000000, 0x00000000, 0x00000000, 73 0x00000000, 0x00000000, 0x00000000, 0x00000000, 74 0x00000000, 0x00000000, 0x00000000, 0x00000000, 75 0x00000000, 0x00000000, 0x00000000, 0x00000000, 76 0x00000000, 0x00000000, 0x00000000, 0x00000000, 77 0x00000000, 0x00000000, 0x00000000, 0x00000000, 78 0x00000000, 0x00000000, 0x00000000, 0x00000000, 79 0x00000000, 0x00000000, 0x00010000, 0x00020304, 80 0x00000004, 0x00000000, 0x00000000, 0x00000000, 81 0x00000000, 0x00000000, 0x00000000, 0x01010000, 82 0x01000000, 0x03030000, 0x00010303, 0x01020202, 83 0x00000000, 0x02040303, 0x21002103, 0x00061200, 84 0x06120612, 0x04320432, 0x04320432, 0x00040004, 85 0x00040004, 0x00000000, 0x00000000, 0x00000000, 86 0x00000000, 0x00010001 87 88 /* 89 * i.MX23 DDR at 133MHz 90 */ 91 #elif defined(CONFIG_MX23) 92 0x01010001, 0x00010100, 0x01000101, 0x00000001, 93 0x00000101, 0x00000000, 0x00010000, 0x01000001, 94 0x00000000, 0x00000001, 0x07000200, 0x00070202, 95 0x02020000, 0x04040a01, 0x00000201, 0x02040000, 96 0x02000000, 0x19000f08, 0x0d0d0000, 0x02021313, 97 0x02061521, 0x0000000a, 0x00080008, 0x00200020, 98 0x00200020, 0x00200020, 0x000003f7, 0x00000000, 99 0x00000000, 0x00000020, 0x00000020, 0x00c80000, 100 0x000a23cd, 0x000000c8, 0x00006665, 0x00000000, 101 0x00000101, 0x00040001, 0x00000000, 0x00000000, 102 0x00010000 103 #else 104 #error Unsupported memory initialization 105 #endif 106 }; 107 108 __weak void mxs_adjust_memory_params(uint32_t *dram_vals) 109 { 110 } 111 112 static void initialize_dram_values(void) 113 { 114 int i; 115 116 mxs_adjust_memory_params(dram_vals); 117 118 for (i = 0; i < ARRAY_SIZE(dram_vals); i++) 119 writel(dram_vals[i], MXS_DRAM_BASE + (4 * i)); 120 121 #ifdef CONFIG_MX23 122 writel((1 << 24), MXS_DRAM_BASE + (4 * 8)); 123 #endif 124 } 125 126 static void mxs_mem_init_clock(void) 127 { 128 struct mxs_clkctrl_regs *clkctrl_regs = 129 (struct mxs_clkctrl_regs *)MXS_CLKCTRL_BASE; 130 #if defined(CONFIG_MX23) 131 /* Fractional divider for ref_emi is 33 ; 480 * 18 / 33 = 266MHz */ 132 const unsigned char divider = 33; 133 #elif defined(CONFIG_MX28) 134 /* Fractional divider for ref_emi is 21 ; 480 * 18 / 21 = 411MHz */ 135 const unsigned char divider = 21; 136 #endif 137 138 /* Gate EMI clock */ 139 writeb(CLKCTRL_FRAC_CLKGATE, 140 &clkctrl_regs->hw_clkctrl_frac0_set[CLKCTRL_FRAC0_EMI]); 141 142 /* Set fractional divider for ref_emi */ 143 writeb(CLKCTRL_FRAC_CLKGATE | (divider & CLKCTRL_FRAC_FRAC_MASK), 144 &clkctrl_regs->hw_clkctrl_frac0[CLKCTRL_FRAC0_EMI]); 145 146 /* Ungate EMI clock */ 147 writeb(CLKCTRL_FRAC_CLKGATE, 148 &clkctrl_regs->hw_clkctrl_frac0_clr[CLKCTRL_FRAC0_EMI]); 149 150 early_delay(11000); 151 152 /* Set EMI clock divider for EMI clock to 411 / 2 = 205MHz */ 153 writel((2 << CLKCTRL_EMI_DIV_EMI_OFFSET) | 154 (1 << CLKCTRL_EMI_DIV_XTAL_OFFSET), 155 &clkctrl_regs->hw_clkctrl_emi); 156 157 /* Unbypass EMI */ 158 writel(CLKCTRL_CLKSEQ_BYPASS_EMI, 159 &clkctrl_regs->hw_clkctrl_clkseq_clr); 160 161 early_delay(10000); 162 } 163 164 static void mxs_mem_setup_cpu_and_hbus(void) 165 { 166 struct mxs_clkctrl_regs *clkctrl_regs = 167 (struct mxs_clkctrl_regs *)MXS_CLKCTRL_BASE; 168 169 /* Set fractional divider for ref_cpu to 480 * 18 / 19 = 454MHz 170 * and ungate CPU clock */ 171 writeb(19 & CLKCTRL_FRAC_FRAC_MASK, 172 (uint8_t *)&clkctrl_regs->hw_clkctrl_frac0[CLKCTRL_FRAC0_CPU]); 173 174 /* Set CPU bypass */ 175 writel(CLKCTRL_CLKSEQ_BYPASS_CPU, 176 &clkctrl_regs->hw_clkctrl_clkseq_set); 177 178 /* HBUS = 151MHz */ 179 writel(CLKCTRL_HBUS_DIV_MASK, &clkctrl_regs->hw_clkctrl_hbus_set); 180 writel(((~3) << CLKCTRL_HBUS_DIV_OFFSET) & CLKCTRL_HBUS_DIV_MASK, 181 &clkctrl_regs->hw_clkctrl_hbus_clr); 182 183 early_delay(10000); 184 185 /* CPU clock divider = 1 */ 186 clrsetbits_le32(&clkctrl_regs->hw_clkctrl_cpu, 187 CLKCTRL_CPU_DIV_CPU_MASK, 1); 188 189 /* Disable CPU bypass */ 190 writel(CLKCTRL_CLKSEQ_BYPASS_CPU, 191 &clkctrl_regs->hw_clkctrl_clkseq_clr); 192 193 early_delay(15000); 194 } 195 196 static void mxs_mem_setup_vdda(void) 197 { 198 struct mxs_power_regs *power_regs = 199 (struct mxs_power_regs *)MXS_POWER_BASE; 200 201 writel((0xc << POWER_VDDACTRL_TRG_OFFSET) | 202 (0x7 << POWER_VDDACTRL_BO_OFFSET_OFFSET) | 203 POWER_VDDACTRL_LINREG_OFFSET_1STEPS_BELOW, 204 &power_regs->hw_power_vddactrl); 205 } 206 207 uint32_t mxs_mem_get_size(void) 208 { 209 uint32_t sz, da; 210 uint32_t *vt = (uint32_t *)0x20; 211 /* The following is "subs pc, r14, #4", used as return from DABT. */ 212 const uint32_t data_abort_memdetect_handler = 0xe25ef004; 213 214 /* Replace the DABT handler. */ 215 da = vt[4]; 216 vt[4] = data_abort_memdetect_handler; 217 218 sz = get_ram_size((long *)PHYS_SDRAM_1, PHYS_SDRAM_1_SIZE); 219 220 /* Restore the old DABT handler. */ 221 vt[4] = da; 222 223 return sz; 224 } 225 226 #ifdef CONFIG_MX23 227 static void mx23_mem_setup_vddmem(void) 228 { 229 struct mxs_power_regs *power_regs = 230 (struct mxs_power_regs *)MXS_POWER_BASE; 231 232 writel((0x12 << POWER_VDDMEMCTRL_TRG_OFFSET) | 233 POWER_VDDMEMCTRL_ENABLE_ILIMIT | 234 POWER_VDDMEMCTRL_ENABLE_LINREG | 235 POWER_VDDMEMCTRL_PULLDOWN_ACTIVE, 236 &power_regs->hw_power_vddmemctrl); 237 238 early_delay(10000); 239 240 writel((0x12 << POWER_VDDMEMCTRL_TRG_OFFSET) | 241 POWER_VDDMEMCTRL_ENABLE_LINREG, 242 &power_regs->hw_power_vddmemctrl); 243 } 244 245 static void mx23_mem_init(void) 246 { 247 mx23_mem_setup_vddmem(); 248 249 /* 250 * Configure the DRAM registers 251 */ 252 253 /* Clear START and SREFRESH bit from DRAM_CTL8 */ 254 clrbits_le32(MXS_DRAM_BASE + 0x20, (1 << 16) | (1 << 8)); 255 256 initialize_dram_values(); 257 258 /* Set START bit in DRAM_CTL16 */ 259 setbits_le32(MXS_DRAM_BASE + 0x20, 1 << 16); 260 261 clrbits_le32(MXS_DRAM_BASE + 0x40, 1 << 17); 262 early_delay(20000); 263 264 /* Adjust EMI port priority. */ 265 clrsetbits_le32(0x80020000, 0x1f << 16, 0x8); 266 early_delay(20000); 267 268 setbits_le32(MXS_DRAM_BASE + 0x40, 1 << 19); 269 setbits_le32(MXS_DRAM_BASE + 0x40, 1 << 11); 270 271 /* Wait for bit 10 (DRAM init complete) in DRAM_CTL18 */ 272 while (!(readl(MXS_DRAM_BASE + 0x48) & (1 << 10))) 273 ; 274 } 275 #endif 276 277 #ifdef CONFIG_MX28 278 static void mx28_mem_init(void) 279 { 280 struct mxs_pinctrl_regs *pinctrl_regs = 281 (struct mxs_pinctrl_regs *)MXS_PINCTRL_BASE; 282 283 /* Set DDR2 mode */ 284 writel(PINCTRL_EMI_DS_CTRL_DDR_MODE_DDR2, 285 &pinctrl_regs->hw_pinctrl_emi_ds_ctrl_set); 286 287 /* 288 * Configure the DRAM registers 289 */ 290 291 /* Clear START bit from DRAM_CTL16 */ 292 clrbits_le32(MXS_DRAM_BASE + 0x40, 1); 293 294 initialize_dram_values(); 295 296 /* Clear SREFRESH bit from DRAM_CTL17 */ 297 clrbits_le32(MXS_DRAM_BASE + 0x44, 1); 298 299 /* Set START bit in DRAM_CTL16 */ 300 setbits_le32(MXS_DRAM_BASE + 0x40, 1); 301 302 /* Wait for bit 20 (DRAM init complete) in DRAM_CTL58 */ 303 while (!(readl(MXS_DRAM_BASE + 0xe8) & (1 << 20))) 304 ; 305 } 306 #endif 307 308 void mxs_mem_init(void) 309 { 310 early_delay(11000); 311 312 mxs_mem_init_clock(); 313 314 mxs_mem_setup_vdda(); 315 316 #if defined(CONFIG_MX23) 317 mx23_mem_init(); 318 #elif defined(CONFIG_MX28) 319 mx28_mem_init(); 320 #endif 321 322 early_delay(10000); 323 324 mxs_mem_setup_cpu_and_hbus(); 325 } 326