1 /* 2 * Freescale i.MX28 RAM init 3 * 4 * Copyright (C) 2011 Marek Vasut <marek.vasut@gmail.com> 5 * on behalf of DENX Software Engineering GmbH 6 * 7 * See file CREDITS for list of people who contributed to this 8 * project. 9 * 10 * This program is free software; you can redistribute it and/or 11 * modify it under the terms of the GNU General Public License as 12 * published by the Free Software Foundation; either version 2 of 13 * the License, or (at your option) any later version. 14 * 15 * This program is distributed in the hope that it will be useful, 16 * but WITHOUT ANY WARRANTY; without even the implied warranty of 17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 18 * GNU General Public License for more details. 19 * 20 * You should have received a copy of the GNU General Public License 21 * along with this program; if not, write to the Free Software 22 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 23 * MA 02111-1307 USA 24 */ 25 26 #include <common.h> 27 #include <config.h> 28 #include <asm/io.h> 29 #include <asm/arch/imx-regs.h> 30 31 #include "mxs_init.h" 32 33 static uint32_t dram_vals[] = { 34 /* 35 * i.MX28 DDR2 at 200MHz 36 */ 37 #if defined(CONFIG_MX28) 38 0x00000000, 0x00000000, 0x00000000, 0x00000000, 39 0x00000000, 0x00000000, 0x00000000, 0x00000000, 40 0x00000000, 0x00000000, 0x00000000, 0x00000000, 41 0x00000000, 0x00000000, 0x00000000, 0x00000000, 42 0x00000000, 0x00000100, 0x00000000, 0x00000000, 43 0x00000000, 0x00000000, 0x00000000, 0x00000000, 44 0x00000000, 0x00000000, 0x00010101, 0x01010101, 45 0x000f0f01, 0x0f02020a, 0x00000000, 0x00010101, 46 0x00000100, 0x00000100, 0x00000000, 0x00000002, 47 0x01010000, 0x05060302, 0x06005003, 0x0a0000c8, 48 0x02009c40, 0x0000030c, 0x0036a609, 0x031a0612, 49 0x02030202, 0x00c8001c, 0x00000000, 0x00000000, 50 0x00012100, 0xffff0303, 0x00012100, 0xffff0303, 51 0x00012100, 0xffff0303, 0x00012100, 0xffff0303, 52 0x00000003, 0x00000000, 0x00000000, 0x00000000, 53 0x00000000, 0x00000000, 0x00000000, 0x00000000, 54 0x00000000, 0x00000000, 0x00000612, 0x01000F02, 55 0x06120612, 0x00000200, 0x00020007, 0xf5014b27, 56 0xf5014b27, 0xf5014b27, 0xf5014b27, 0x07000300, 57 0x07000300, 0x07000300, 0x07000300, 0x00000006, 58 0x00000000, 0x00000000, 0x01000000, 0x01020408, 59 0x08040201, 0x000f1133, 0x00000000, 0x00001f04, 60 0x00001f04, 0x00001f04, 0x00001f04, 0x00001f04, 61 0x00001f04, 0x00001f04, 0x00001f04, 0x00000000, 62 0x00000000, 0x00000000, 0x00000000, 0x00000000, 63 0x00000000, 0x00000000, 0x00000000, 0x00000000, 64 0x00000000, 0x00000000, 0x00000000, 0x00000000, 65 0x00000000, 0x00000000, 0x00000000, 0x00000000, 66 0x00000000, 0x00000000, 0x00000000, 0x00000000, 67 0x00000000, 0x00000000, 0x00000000, 0x00000000, 68 0x00000000, 0x00000000, 0x00000000, 0x00000000, 69 0x00000000, 0x00000000, 0x00000000, 0x00000000, 70 0x00000000, 0x00000000, 0x00000000, 0x00000000, 71 0x00000000, 0x00000000, 0x00000000, 0x00000000, 72 0x00000000, 0x00000000, 0x00000000, 0x00000000, 73 0x00000000, 0x00000000, 0x00000000, 0x00000000, 74 0x00000000, 0x00000000, 0x00000000, 0x00000000, 75 0x00000000, 0x00000000, 0x00000000, 0x00000000, 76 0x00000000, 0x00000000, 0x00000000, 0x00000000, 77 0x00000000, 0x00000000, 0x00000000, 0x00000000, 78 0x00000000, 0x00000000, 0x00010000, 0x00020304, 79 0x00000004, 0x00000000, 0x00000000, 0x00000000, 80 0x00000000, 0x00000000, 0x00000000, 0x01010000, 81 0x01000000, 0x03030000, 0x00010303, 0x01020202, 82 0x00000000, 0x02040303, 0x21002103, 0x00061200, 83 0x06120612, 0x04320432, 0x04320432, 0x00040004, 84 0x00040004, 0x00000000, 0x00000000, 0x00000000, 85 0x00000000, 0x00010001 86 87 /* 88 * i.MX23 DDR at 133MHz 89 */ 90 #elif defined(CONFIG_MX23) 91 0x01010001, 0x00010100, 0x01000101, 0x00000001, 92 0x00000101, 0x00000000, 0x00010000, 0x01000001, 93 0x00000000, 0x00000001, 0x07000200, 0x00070202, 94 0x02020000, 0x04040a01, 0x00000201, 0x02040000, 95 0x02000000, 0x19000f08, 0x0d0d0000, 0x02021313, 96 0x02061521, 0x0000000a, 0x00080008, 0x00200020, 97 0x00200020, 0x00200020, 0x000003f7, 0x00000000, 98 0x00000000, 0x00000020, 0x00000020, 0x00c80000, 99 0x000a23cd, 0x000000c8, 0x00006665, 0x00000000, 100 0x00000101, 0x00040001, 0x00000000, 0x00000000, 101 0x00010000 102 #else 103 #error Unsupported memory initialization 104 #endif 105 }; 106 107 void __mxs_adjust_memory_params(uint32_t *dram_vals) 108 { 109 } 110 void mxs_adjust_memory_params(uint32_t *dram_vals) 111 __attribute__((weak, alias("__mxs_adjust_memory_params"))); 112 113 static void initialize_dram_values(void) 114 { 115 int i; 116 117 mxs_adjust_memory_params(dram_vals); 118 119 for (i = 0; i < ARRAY_SIZE(dram_vals); i++) 120 writel(dram_vals[i], MXS_DRAM_BASE + (4 * i)); 121 122 #ifdef CONFIG_MX23 123 writel((1 << 24), MXS_DRAM_BASE + (4 * 8)); 124 #endif 125 } 126 127 static void mxs_mem_init_clock(void) 128 { 129 struct mxs_clkctrl_regs *clkctrl_regs = 130 (struct mxs_clkctrl_regs *)MXS_CLKCTRL_BASE; 131 #if defined(CONFIG_MX23) 132 /* Fractional divider for ref_emi is 33 ; 480 * 18 / 33 = 266MHz */ 133 const unsigned char divider = 33; 134 #elif defined(CONFIG_MX28) 135 /* Fractional divider for ref_emi is 21 ; 480 * 18 / 21 = 411MHz */ 136 const unsigned char divider = 21; 137 #endif 138 139 /* Gate EMI clock */ 140 writeb(CLKCTRL_FRAC_CLKGATE, 141 &clkctrl_regs->hw_clkctrl_frac0_set[CLKCTRL_FRAC0_EMI]); 142 143 /* Set fractional divider for ref_emi */ 144 writeb(CLKCTRL_FRAC_CLKGATE | (divider & CLKCTRL_FRAC_FRAC_MASK), 145 &clkctrl_regs->hw_clkctrl_frac0[CLKCTRL_FRAC0_EMI]); 146 147 /* Ungate EMI clock */ 148 writeb(CLKCTRL_FRAC_CLKGATE, 149 &clkctrl_regs->hw_clkctrl_frac0_clr[CLKCTRL_FRAC0_EMI]); 150 151 early_delay(11000); 152 153 /* Set EMI clock divider for EMI clock to 411 / 2 = 205MHz */ 154 writel((2 << CLKCTRL_EMI_DIV_EMI_OFFSET) | 155 (1 << CLKCTRL_EMI_DIV_XTAL_OFFSET), 156 &clkctrl_regs->hw_clkctrl_emi); 157 158 /* Unbypass EMI */ 159 writel(CLKCTRL_CLKSEQ_BYPASS_EMI, 160 &clkctrl_regs->hw_clkctrl_clkseq_clr); 161 162 early_delay(10000); 163 } 164 165 static void mxs_mem_setup_cpu_and_hbus(void) 166 { 167 struct mxs_clkctrl_regs *clkctrl_regs = 168 (struct mxs_clkctrl_regs *)MXS_CLKCTRL_BASE; 169 170 /* Set fractional divider for ref_cpu to 480 * 18 / 19 = 454MHz 171 * and ungate CPU clock */ 172 writeb(19 & CLKCTRL_FRAC_FRAC_MASK, 173 (uint8_t *)&clkctrl_regs->hw_clkctrl_frac0[CLKCTRL_FRAC0_CPU]); 174 175 /* Set CPU bypass */ 176 writel(CLKCTRL_CLKSEQ_BYPASS_CPU, 177 &clkctrl_regs->hw_clkctrl_clkseq_set); 178 179 /* HBUS = 151MHz */ 180 writel(CLKCTRL_HBUS_DIV_MASK, &clkctrl_regs->hw_clkctrl_hbus_set); 181 writel(((~3) << CLKCTRL_HBUS_DIV_OFFSET) & CLKCTRL_HBUS_DIV_MASK, 182 &clkctrl_regs->hw_clkctrl_hbus_clr); 183 184 early_delay(10000); 185 186 /* CPU clock divider = 1 */ 187 clrsetbits_le32(&clkctrl_regs->hw_clkctrl_cpu, 188 CLKCTRL_CPU_DIV_CPU_MASK, 1); 189 190 /* Disable CPU bypass */ 191 writel(CLKCTRL_CLKSEQ_BYPASS_CPU, 192 &clkctrl_regs->hw_clkctrl_clkseq_clr); 193 194 early_delay(15000); 195 } 196 197 static void mxs_mem_setup_vdda(void) 198 { 199 struct mxs_power_regs *power_regs = 200 (struct mxs_power_regs *)MXS_POWER_BASE; 201 202 writel((0xc << POWER_VDDACTRL_TRG_OFFSET) | 203 (0x7 << POWER_VDDACTRL_BO_OFFSET_OFFSET) | 204 POWER_VDDACTRL_LINREG_OFFSET_1STEPS_BELOW, 205 &power_regs->hw_power_vddactrl); 206 } 207 208 uint32_t mxs_mem_get_size(void) 209 { 210 uint32_t sz, da; 211 uint32_t *vt = (uint32_t *)0x20; 212 /* The following is "subs pc, r14, #4", used as return from DABT. */ 213 const uint32_t data_abort_memdetect_handler = 0xe25ef004; 214 215 /* Replace the DABT handler. */ 216 da = vt[4]; 217 vt[4] = data_abort_memdetect_handler; 218 219 sz = get_ram_size((long *)PHYS_SDRAM_1, PHYS_SDRAM_1_SIZE); 220 221 /* Restore the old DABT handler. */ 222 vt[4] = da; 223 224 return sz; 225 } 226 227 #ifdef CONFIG_MX23 228 static void mx23_mem_setup_vddmem(void) 229 { 230 struct mxs_power_regs *power_regs = 231 (struct mxs_power_regs *)MXS_POWER_BASE; 232 233 writel((0x12 << POWER_VDDMEMCTRL_TRG_OFFSET) | 234 POWER_VDDMEMCTRL_ENABLE_ILIMIT | 235 POWER_VDDMEMCTRL_ENABLE_LINREG | 236 POWER_VDDMEMCTRL_PULLDOWN_ACTIVE, 237 &power_regs->hw_power_vddmemctrl); 238 239 early_delay(10000); 240 241 writel((0x12 << POWER_VDDMEMCTRL_TRG_OFFSET) | 242 POWER_VDDMEMCTRL_ENABLE_LINREG, 243 &power_regs->hw_power_vddmemctrl); 244 } 245 246 static void mx23_mem_init(void) 247 { 248 mx23_mem_setup_vddmem(); 249 250 /* 251 * Configure the DRAM registers 252 */ 253 254 /* Clear START and SREFRESH bit from DRAM_CTL8 */ 255 clrbits_le32(MXS_DRAM_BASE + 0x20, (1 << 16) | (1 << 8)); 256 257 initialize_dram_values(); 258 259 /* Set START bit in DRAM_CTL16 */ 260 setbits_le32(MXS_DRAM_BASE + 0x20, 1 << 16); 261 262 clrbits_le32(MXS_DRAM_BASE + 0x40, 1 << 17); 263 early_delay(20000); 264 265 /* Adjust EMI port priority. */ 266 clrsetbits_le32(0x80020000, 0x1f << 16, 0x8); 267 early_delay(20000); 268 269 setbits_le32(MXS_DRAM_BASE + 0x40, 1 << 19); 270 setbits_le32(MXS_DRAM_BASE + 0x40, 1 << 11); 271 272 /* Wait for bit 10 (DRAM init complete) in DRAM_CTL18 */ 273 while (!(readl(MXS_DRAM_BASE + 0x48) & (1 << 10))) 274 ; 275 } 276 #endif 277 278 #ifdef CONFIG_MX28 279 static void mx28_mem_init(void) 280 { 281 struct mxs_pinctrl_regs *pinctrl_regs = 282 (struct mxs_pinctrl_regs *)MXS_PINCTRL_BASE; 283 284 /* Set DDR2 mode */ 285 writel(PINCTRL_EMI_DS_CTRL_DDR_MODE_DDR2, 286 &pinctrl_regs->hw_pinctrl_emi_ds_ctrl_set); 287 288 /* 289 * Configure the DRAM registers 290 */ 291 292 /* Clear START bit from DRAM_CTL16 */ 293 clrbits_le32(MXS_DRAM_BASE + 0x40, 1); 294 295 initialize_dram_values(); 296 297 /* Clear SREFRESH bit from DRAM_CTL17 */ 298 clrbits_le32(MXS_DRAM_BASE + 0x44, 1); 299 300 /* Set START bit in DRAM_CTL16 */ 301 setbits_le32(MXS_DRAM_BASE + 0x40, 1); 302 303 /* Wait for bit 20 (DRAM init complete) in DRAM_CTL58 */ 304 while (!(readl(MXS_DRAM_BASE + 0xe8) & (1 << 20))) 305 ; 306 } 307 #endif 308 309 void mxs_mem_init(void) 310 { 311 early_delay(11000); 312 313 mxs_mem_init_clock(); 314 315 mxs_mem_setup_vdda(); 316 317 #if defined(CONFIG_MX23) 318 mx23_mem_init(); 319 #elif defined(CONFIG_MX28) 320 mx28_mem_init(); 321 #endif 322 323 early_delay(10000); 324 325 mxs_mem_setup_cpu_and_hbus(); 326 } 327