1 /* 2 * Freescale i.MX28 RAM init 3 * 4 * Copyright (C) 2011 Marek Vasut <marek.vasut@gmail.com> 5 * on behalf of DENX Software Engineering GmbH 6 * 7 * See file CREDITS for list of people who contributed to this 8 * project. 9 * 10 * This program is free software; you can redistribute it and/or 11 * modify it under the terms of the GNU General Public License as 12 * published by the Free Software Foundation; either version 2 of 13 * the License, or (at your option) any later version. 14 * 15 * This program is distributed in the hope that it will be useful, 16 * but WITHOUT ANY WARRANTY; without even the implied warranty of 17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 18 * GNU General Public License for more details. 19 * 20 * You should have received a copy of the GNU General Public License 21 * along with this program; if not, write to the Free Software 22 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 23 * MA 02111-1307 USA 24 */ 25 26 #include <common.h> 27 #include <config.h> 28 #include <asm/io.h> 29 #include <asm/arch/iomux-mx28.h> 30 #include <asm/arch/imx-regs.h> 31 32 #include "mxs_init.h" 33 34 static uint32_t mx28_dram_vals[] = { 35 0x00000000, 0x00000000, 0x00000000, 0x00000000, 36 0x00000000, 0x00000000, 0x00000000, 0x00000000, 37 0x00000000, 0x00000000, 0x00000000, 0x00000000, 38 0x00000000, 0x00000000, 0x00000000, 0x00000000, 39 0x00000000, 0x00000100, 0x00000000, 0x00000000, 40 0x00000000, 0x00000000, 0x00000000, 0x00000000, 41 0x00000000, 0x00000000, 0x00010101, 0x01010101, 42 0x000f0f01, 0x0f02020a, 0x00000000, 0x00010101, 43 0x00000100, 0x00000100, 0x00000000, 0x00000002, 44 0x01010000, 0x05060302, 0x06005003, 0x0a0000c8, 45 0x02009c40, 0x0000030c, 0x0036a609, 0x031a0612, 46 0x02030202, 0x00c8001c, 0x00000000, 0x00000000, 47 0x00012100, 0xffff0303, 0x00012100, 0xffff0303, 48 0x00012100, 0xffff0303, 0x00012100, 0xffff0303, 49 0x00000003, 0x00000000, 0x00000000, 0x00000000, 50 0x00000000, 0x00000000, 0x00000000, 0x00000000, 51 0x00000000, 0x00000000, 0x00000612, 0x01000F02, 52 0x06120612, 0x00000200, 0x00020007, 0xf5014b27, 53 0xf5014b27, 0xf5014b27, 0xf5014b27, 0x07000300, 54 0x07000300, 0x07000300, 0x07000300, 0x00000006, 55 0x00000000, 0x00000000, 0x01000000, 0x01020408, 56 0x08040201, 0x000f1133, 0x00000000, 0x00001f04, 57 0x00001f04, 0x00001f04, 0x00001f04, 0x00001f04, 58 0x00001f04, 0x00001f04, 0x00001f04, 0x00000000, 59 0x00000000, 0x00000000, 0x00000000, 0x00000000, 60 0x00000000, 0x00000000, 0x00000000, 0x00000000, 61 0x00000000, 0x00000000, 0x00000000, 0x00000000, 62 0x00000000, 0x00000000, 0x00000000, 0x00000000, 63 0x00000000, 0x00000000, 0x00000000, 0x00000000, 64 0x00000000, 0x00000000, 0x00000000, 0x00000000, 65 0x00000000, 0x00000000, 0x00000000, 0x00000000, 66 0x00000000, 0x00000000, 0x00000000, 0x00000000, 67 0x00000000, 0x00000000, 0x00000000, 0x00000000, 68 0x00000000, 0x00000000, 0x00000000, 0x00000000, 69 0x00000000, 0x00000000, 0x00000000, 0x00000000, 70 0x00000000, 0x00000000, 0x00000000, 0x00000000, 71 0x00000000, 0x00000000, 0x00000000, 0x00000000, 72 0x00000000, 0x00000000, 0x00000000, 0x00000000, 73 0x00000000, 0x00000000, 0x00000000, 0x00000000, 74 0x00000000, 0x00000000, 0x00000000, 0x00000000, 75 0x00000000, 0x00000000, 0x00010000, 0x00020304, 76 0x00000004, 0x00000000, 0x00000000, 0x00000000, 77 0x00000000, 0x00000000, 0x00000000, 0x01010000, 78 0x01000000, 0x03030000, 0x00010303, 0x01020202, 79 0x00000000, 0x02040303, 0x21002103, 0x00061200, 80 0x06120612, 0x04320432, 0x04320432, 0x00040004, 81 0x00040004, 0x00000000, 0x00000000, 0x00000000, 82 0x00000000, 0x00010001 83 }; 84 85 void __mxs_adjust_memory_params(uint32_t *dram_vals) 86 { 87 } 88 void mxs_adjust_memory_params(uint32_t *dram_vals) 89 __attribute__((weak, alias("__mxs_adjust_memory_params"))); 90 91 void init_mx28_200mhz_ddr2(void) 92 { 93 int i; 94 95 mxs_adjust_memory_params(mx28_dram_vals); 96 97 for (i = 0; i < ARRAY_SIZE(mx28_dram_vals); i++) 98 writel(mx28_dram_vals[i], MXS_DRAM_BASE + (4 * i)); 99 } 100 101 void mxs_mem_init_clock(void) 102 { 103 struct mxs_clkctrl_regs *clkctrl_regs = 104 (struct mxs_clkctrl_regs *)MXS_CLKCTRL_BASE; 105 106 /* Gate EMI clock */ 107 writeb(CLKCTRL_FRAC_CLKGATE, 108 &clkctrl_regs->hw_clkctrl_frac0_set[CLKCTRL_FRAC0_EMI]); 109 110 /* Set fractional divider for ref_emi to 480 * 18 / 21 = 411MHz */ 111 writeb(CLKCTRL_FRAC_CLKGATE | (21 & CLKCTRL_FRAC_FRAC_MASK), 112 &clkctrl_regs->hw_clkctrl_frac0[CLKCTRL_FRAC0_EMI]); 113 114 /* Ungate EMI clock */ 115 writeb(CLKCTRL_FRAC_CLKGATE, 116 &clkctrl_regs->hw_clkctrl_frac0_clr[CLKCTRL_FRAC0_EMI]); 117 118 early_delay(11000); 119 120 /* Set EMI clock divider for EMI clock to 411 / 2 = 205MHz */ 121 writel((2 << CLKCTRL_EMI_DIV_EMI_OFFSET) | 122 (1 << CLKCTRL_EMI_DIV_XTAL_OFFSET), 123 &clkctrl_regs->hw_clkctrl_emi); 124 125 /* Unbypass EMI */ 126 writel(CLKCTRL_CLKSEQ_BYPASS_EMI, 127 &clkctrl_regs->hw_clkctrl_clkseq_clr); 128 129 early_delay(10000); 130 } 131 132 void mxs_mem_setup_cpu_and_hbus(void) 133 { 134 struct mxs_clkctrl_regs *clkctrl_regs = 135 (struct mxs_clkctrl_regs *)MXS_CLKCTRL_BASE; 136 137 /* Set fractional divider for ref_cpu to 480 * 18 / 19 = 454MHz 138 * and ungate CPU clock */ 139 writeb(19 & CLKCTRL_FRAC_FRAC_MASK, 140 (uint8_t *)&clkctrl_regs->hw_clkctrl_frac0[CLKCTRL_FRAC0_CPU]); 141 142 /* Set CPU bypass */ 143 writel(CLKCTRL_CLKSEQ_BYPASS_CPU, 144 &clkctrl_regs->hw_clkctrl_clkseq_set); 145 146 /* HBUS = 151MHz */ 147 writel(CLKCTRL_HBUS_DIV_MASK, &clkctrl_regs->hw_clkctrl_hbus_set); 148 writel(((~3) << CLKCTRL_HBUS_DIV_OFFSET) & CLKCTRL_HBUS_DIV_MASK, 149 &clkctrl_regs->hw_clkctrl_hbus_clr); 150 151 early_delay(10000); 152 153 /* CPU clock divider = 1 */ 154 clrsetbits_le32(&clkctrl_regs->hw_clkctrl_cpu, 155 CLKCTRL_CPU_DIV_CPU_MASK, 1); 156 157 /* Disable CPU bypass */ 158 writel(CLKCTRL_CLKSEQ_BYPASS_CPU, 159 &clkctrl_regs->hw_clkctrl_clkseq_clr); 160 161 early_delay(15000); 162 } 163 164 void mxs_mem_setup_vdda(void) 165 { 166 struct mxs_power_regs *power_regs = 167 (struct mxs_power_regs *)MXS_POWER_BASE; 168 169 writel((0xc << POWER_VDDACTRL_TRG_OFFSET) | 170 (0x7 << POWER_VDDACTRL_BO_OFFSET_OFFSET) | 171 POWER_VDDACTRL_LINREG_OFFSET_1STEPS_BELOW, 172 &power_regs->hw_power_vddactrl); 173 } 174 175 void mxs_mem_setup_vddd(void) 176 { 177 struct mxs_power_regs *power_regs = 178 (struct mxs_power_regs *)MXS_POWER_BASE; 179 180 writel((0x1c << POWER_VDDDCTRL_TRG_OFFSET) | 181 (0x7 << POWER_VDDDCTRL_BO_OFFSET_OFFSET) | 182 POWER_VDDDCTRL_LINREG_OFFSET_1STEPS_BELOW, 183 &power_regs->hw_power_vdddctrl); 184 } 185 186 uint32_t mxs_mem_get_size(void) 187 { 188 uint32_t sz, da; 189 uint32_t *vt = (uint32_t *)0x20; 190 /* The following is "subs pc, r14, #4", used as return from DABT. */ 191 const uint32_t data_abort_memdetect_handler = 0xe25ef004; 192 193 /* Replace the DABT handler. */ 194 da = vt[4]; 195 vt[4] = data_abort_memdetect_handler; 196 197 sz = get_ram_size((long *)PHYS_SDRAM_1, PHYS_SDRAM_1_SIZE); 198 199 /* Restore the old DABT handler. */ 200 vt[4] = da; 201 202 return sz; 203 } 204 205 void mxs_mem_init(void) 206 { 207 struct mxs_clkctrl_regs *clkctrl_regs = 208 (struct mxs_clkctrl_regs *)MXS_CLKCTRL_BASE; 209 struct mxs_pinctrl_regs *pinctrl_regs = 210 (struct mxs_pinctrl_regs *)MXS_PINCTRL_BASE; 211 212 /* Set DDR2 mode */ 213 writel(PINCTRL_EMI_DS_CTRL_DDR_MODE_DDR2, 214 &pinctrl_regs->hw_pinctrl_emi_ds_ctrl_set); 215 216 /* Power up PLL0 */ 217 writel(CLKCTRL_PLL0CTRL0_POWER, 218 &clkctrl_regs->hw_clkctrl_pll0ctrl0_set); 219 220 early_delay(11000); 221 222 mxs_mem_init_clock(); 223 224 mxs_mem_setup_vdda(); 225 226 /* 227 * Configure the DRAM registers 228 */ 229 230 /* Clear START bit from DRAM_CTL16 */ 231 clrbits_le32(MXS_DRAM_BASE + 0x40, 1); 232 233 init_mx28_200mhz_ddr2(); 234 235 /* Clear SREFRESH bit from DRAM_CTL17 */ 236 clrbits_le32(MXS_DRAM_BASE + 0x44, 1); 237 238 /* Set START bit in DRAM_CTL16 */ 239 setbits_le32(MXS_DRAM_BASE + 0x40, 1); 240 241 /* Wait for bit 20 (DRAM init complete) in DRAM_CTL58 */ 242 while (!(readl(MXS_DRAM_BASE + 0xe8) & (1 << 20))) 243 ; 244 245 mxs_mem_setup_vddd(); 246 247 early_delay(10000); 248 249 mxs_mem_setup_cpu_and_hbus(); 250 } 251