1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3  * Freescale i.MX28 RAM init
4  *
5  * Copyright (C) 2011 Marek Vasut <marek.vasut@gmail.com>
6  * on behalf of DENX Software Engineering GmbH
7  */
8 
9 #include <common.h>
10 #include <config.h>
11 #include <asm/io.h>
12 #include <asm/arch/imx-regs.h>
13 #include <asm/arch/sys_proto.h>
14 #include <linux/compiler.h>
15 
16 #include "mxs_init.h"
17 
18 static uint32_t dram_vals[] = {
19 /*
20  * i.MX28 DDR2 at 200MHz
21  */
22 #if defined(CONFIG_MX28)
23 	0x00000000, 0x00000000, 0x00000000, 0x00000000,
24 	0x00000000, 0x00000000, 0x00000000, 0x00000000,
25 	0x00000000, 0x00000000, 0x00000000, 0x00000000,
26 	0x00000000, 0x00000000, 0x00000000, 0x00000000,
27 	0x00000000, 0x00000100, 0x00000000, 0x00000000,
28 	0x00000000, 0x00000000, 0x00000000, 0x00000000,
29 	0x00000000, 0x00000000, 0x00010101, 0x01010101,
30 	0x000f0f01, 0x0f02020a, 0x00000000, 0x00010101,
31 	0x00000100, 0x00000100, 0x00000000, 0x00000002,
32 	0x01010000, 0x07080403, 0x06005003, 0x0a0000c8,
33 	0x02009c40, 0x0002030c, 0x0036a609, 0x031a0612,
34 	0x02030202, 0x00c8001c, 0x00000000, 0x00000000,
35 	0x00012100, 0xffff0303, 0x00012100, 0xffff0303,
36 	0x00012100, 0xffff0303, 0x00012100, 0xffff0303,
37 	0x00000003, 0x00000000, 0x00000000, 0x00000000,
38 	0x00000000, 0x00000000, 0x00000000, 0x00000000,
39 	0x00000000, 0x00000000, 0x00000612, 0x01000F02,
40 	0x06120612, 0x00000200, 0x00020007, 0xf4004a27,
41 	0xf4004a27, 0xf4004a27, 0xf4004a27, 0x07000300,
42 	0x07000300, 0x07400300, 0x07400300, 0x00000005,
43 	0x00000000, 0x00000000, 0x01000000, 0x01020408,
44 	0x08040201, 0x000f1133, 0x00000000, 0x00001f04,
45 	0x00001f04, 0x00001f04, 0x00001f04, 0x00001f04,
46 	0x00001f04, 0x00001f04, 0x00001f04, 0x00000000,
47 	0x00000000, 0x00000000, 0x00000000, 0x00000000,
48 	0x00000000, 0x00000000, 0x00000000, 0x00000000,
49 	0x00000000, 0x00000000, 0x00000000, 0x00000000,
50 	0x00000000, 0x00000000, 0x00000000, 0x00000000,
51 	0x00000000, 0x00000000, 0x00000000, 0x00000000,
52 	0x00000000, 0x00000000, 0x00000000, 0x00000000,
53 	0x00000000, 0x00000000, 0x00000000, 0x00000000,
54 	0x00000000, 0x00000000, 0x00000000, 0x00000000,
55 	0x00000000, 0x00000000, 0x00000000, 0x00000000,
56 	0x00000000, 0x00000000, 0x00000000, 0x00000000,
57 	0x00000000, 0x00000000, 0x00000000, 0x00000000,
58 	0x00000000, 0x00000000, 0x00000000, 0x00000000,
59 	0x00000000, 0x00000000, 0x00000000, 0x00000000,
60 	0x00000000, 0x00000000, 0x00000000, 0x00000000,
61 	0x00000000, 0x00000000, 0x00000000, 0x00000000,
62 	0x00000000, 0x00000000, 0x00000000, 0x00000000,
63 	0x00000000, 0x00000000, 0x00010000, 0x00030404,
64 	0x00000003, 0x00000000, 0x00000000, 0x00000000,
65 	0x00000000, 0x00000000, 0x00000000, 0x01010000,
66 	0x01000000, 0x03030000, 0x00010303, 0x01020202,
67 	0x00000000, 0x02040303, 0x21002103, 0x00061200,
68 	0x06120612, 0x04420442, 0x04420442, 0x00040004,
69 	0x00040004, 0x00000000, 0x00000000, 0x00000000,
70 	0x00000000, 0xffffffff
71 
72 /*
73  * i.MX23 DDR at 133MHz
74  */
75 #elif defined(CONFIG_MX23)
76 	0x01010001, 0x00010100, 0x01000101, 0x00000001,
77 	0x00000101, 0x00000000, 0x00010000, 0x01000001,
78 	0x00000000, 0x00000001, 0x07000200, 0x00070202,
79 	0x02020000, 0x04040a01, 0x00000201, 0x02040000,
80 	0x02000000, 0x19000f08, 0x0d0d0000, 0x02021313,
81 	0x02061521, 0x0000000a, 0x00080008, 0x00200020,
82 	0x00200020, 0x00200020, 0x000003f7, 0x00000000,
83 	0x00000000, 0x00000020, 0x00000020, 0x00c80000,
84 	0x000a23cd, 0x000000c8, 0x00006665, 0x00000000,
85 	0x00000101, 0x00040001, 0x00000000, 0x00000000,
86 	0x00010000
87 #else
88 #error Unsupported memory initialization
89 #endif
90 };
91 
92 __weak void mxs_adjust_memory_params(uint32_t *dram_vals)
93 {
94 	debug("SPL: Using default SDRAM parameters\n");
95 }
96 
97 #ifdef CONFIG_MX28
98 static void initialize_dram_values(void)
99 {
100 	int i;
101 
102 	debug("SPL: Setting mx28 board specific SDRAM parameters\n");
103 	mxs_adjust_memory_params(dram_vals);
104 
105 	debug("SPL: Applying SDRAM parameters\n");
106 	for (i = 0; i < ARRAY_SIZE(dram_vals); i++)
107 		writel(dram_vals[i], MXS_DRAM_BASE + (4 * i));
108 }
109 #else
110 static void initialize_dram_values(void)
111 {
112 	int i;
113 
114 	debug("SPL: Setting mx23 board specific SDRAM parameters\n");
115 	mxs_adjust_memory_params(dram_vals);
116 
117 	/*
118 	 * HW_DRAM_CTL27, HW_DRAM_CTL28 and HW_DRAM_CTL35 are not initialized as
119 	 * per FSL bootlets code.
120 	 *
121 	 * mx23 Reference Manual marks HW_DRAM_CTL27 and HW_DRAM_CTL28 as
122 	 * "reserved".
123 	 * HW_DRAM_CTL8 is setup as the last element.
124 	 * So skip the initialization of these HW_DRAM_CTL registers.
125 	 */
126 	debug("SPL: Applying SDRAM parameters\n");
127 	for (i = 0; i < ARRAY_SIZE(dram_vals); i++) {
128 		if (i == 8 || i == 27 || i == 28 || i == 35)
129 			continue;
130 		writel(dram_vals[i], MXS_DRAM_BASE + (4 * i));
131 	}
132 
133 	/*
134 	 * Enable tRAS lockout in HW_DRAM_CTL08 ; it must be the last
135 	 * element to be set
136 	 */
137 	writel((1 << 24), MXS_DRAM_BASE + (4 * 8));
138 }
139 #endif
140 
141 static void mxs_mem_init_clock(void)
142 {
143 	struct mxs_clkctrl_regs *clkctrl_regs =
144 		(struct mxs_clkctrl_regs *)MXS_CLKCTRL_BASE;
145 #if defined(CONFIG_MX23)
146 	/* Fractional divider for ref_emi is 33 ; 480 * 18 / 33 = 266MHz */
147 	const unsigned char divider = 33;
148 #elif defined(CONFIG_MX28)
149 	/* Fractional divider for ref_emi is 21 ; 480 * 18 / 21 = 411MHz */
150 	const unsigned char divider = 21;
151 #endif
152 
153 	debug("SPL: Initialising FRAC0\n");
154 
155 	/* Gate EMI clock */
156 	writeb(CLKCTRL_FRAC_CLKGATE,
157 		&clkctrl_regs->hw_clkctrl_frac0_set[CLKCTRL_FRAC0_EMI]);
158 
159 	/* Set fractional divider for ref_emi */
160 	writeb(CLKCTRL_FRAC_CLKGATE | (divider & CLKCTRL_FRAC_FRAC_MASK),
161 		&clkctrl_regs->hw_clkctrl_frac0[CLKCTRL_FRAC0_EMI]);
162 
163 	/* Ungate EMI clock */
164 	writeb(CLKCTRL_FRAC_CLKGATE,
165 		&clkctrl_regs->hw_clkctrl_frac0_clr[CLKCTRL_FRAC0_EMI]);
166 
167 	early_delay(11000);
168 
169 	/* Set EMI clock divider for EMI clock to 411 / 2 = 205MHz */
170 	writel((2 << CLKCTRL_EMI_DIV_EMI_OFFSET) |
171 		(1 << CLKCTRL_EMI_DIV_XTAL_OFFSET),
172 		&clkctrl_regs->hw_clkctrl_emi);
173 
174 	/* Unbypass EMI */
175 	writel(CLKCTRL_CLKSEQ_BYPASS_EMI,
176 		&clkctrl_regs->hw_clkctrl_clkseq_clr);
177 
178 	early_delay(10000);
179 	debug("SPL: FRAC0 Initialised\n");
180 }
181 
182 static void mxs_mem_setup_cpu_and_hbus(void)
183 {
184 	struct mxs_clkctrl_regs *clkctrl_regs =
185 		(struct mxs_clkctrl_regs *)MXS_CLKCTRL_BASE;
186 
187 	debug("SPL: Setting CPU and HBUS clock frequencies\n");
188 
189 	/* Set fractional divider for ref_cpu to 480 * 18 / 19 = 454MHz
190 	 * and ungate CPU clock */
191 	writeb(19 & CLKCTRL_FRAC_FRAC_MASK,
192 		(uint8_t *)&clkctrl_regs->hw_clkctrl_frac0[CLKCTRL_FRAC0_CPU]);
193 
194 	/* Set CPU bypass */
195 	writel(CLKCTRL_CLKSEQ_BYPASS_CPU,
196 		&clkctrl_regs->hw_clkctrl_clkseq_set);
197 
198 	/* HBUS = 151MHz */
199 	writel(CLKCTRL_HBUS_DIV_MASK, &clkctrl_regs->hw_clkctrl_hbus_set);
200 	writel(((~3) << CLKCTRL_HBUS_DIV_OFFSET) & CLKCTRL_HBUS_DIV_MASK,
201 		&clkctrl_regs->hw_clkctrl_hbus_clr);
202 
203 	early_delay(10000);
204 
205 	/* CPU clock divider = 1 */
206 	clrsetbits_le32(&clkctrl_regs->hw_clkctrl_cpu,
207 			CLKCTRL_CPU_DIV_CPU_MASK, 1);
208 
209 	/* Disable CPU bypass */
210 	writel(CLKCTRL_CLKSEQ_BYPASS_CPU,
211 		&clkctrl_regs->hw_clkctrl_clkseq_clr);
212 
213 	early_delay(15000);
214 }
215 
216 static void mxs_mem_setup_vdda(void)
217 {
218 	struct mxs_power_regs *power_regs =
219 		(struct mxs_power_regs *)MXS_POWER_BASE;
220 
221 	debug("SPL: Configuring VDDA\n");
222 
223 	writel((0xc << POWER_VDDACTRL_TRG_OFFSET) |
224 		(0x7 << POWER_VDDACTRL_BO_OFFSET_OFFSET) |
225 		POWER_VDDACTRL_LINREG_OFFSET_1STEPS_BELOW,
226 		&power_regs->hw_power_vddactrl);
227 }
228 
229 uint32_t mxs_mem_get_size(void)
230 {
231 	uint32_t sz, da;
232 	uint32_t *vt = (uint32_t *)0x20;
233 	/* The following is "subs pc, r14, #4", used as return from DABT. */
234 	const uint32_t data_abort_memdetect_handler = 0xe25ef004;
235 
236 	/* Replace the DABT handler. */
237 	da = vt[4];
238 	vt[4] = data_abort_memdetect_handler;
239 
240 	sz = get_ram_size((long *)PHYS_SDRAM_1, PHYS_SDRAM_1_SIZE);
241 
242 	/* Restore the old DABT handler. */
243 	vt[4] = da;
244 
245 	return sz;
246 }
247 
248 #ifdef CONFIG_MX23
249 static void mx23_mem_setup_vddmem(void)
250 {
251 	struct mxs_power_regs *power_regs =
252 		(struct mxs_power_regs *)MXS_POWER_BASE;
253 
254 	debug("SPL: Setting mx23 VDDMEM\n");
255 
256 	/* We must wait before and after disabling the current limiter! */
257 	early_delay(10000);
258 
259 	clrbits_le32(&power_regs->hw_power_vddmemctrl,
260 		POWER_VDDMEMCTRL_ENABLE_ILIMIT);
261 
262 	early_delay(10000);
263 
264 }
265 
266 static void mx23_mem_init(void)
267 {
268 	debug("SPL: Initialising mx23 SDRAM Controller\n");
269 
270 	/*
271 	 * Reset/ungate the EMI block. This is essential, otherwise the system
272 	 * suffers from memory instability. This thing is mx23 specific and is
273 	 * no longer present on mx28.
274 	 */
275 	mxs_reset_block((struct mxs_register_32 *)MXS_EMI_BASE);
276 
277 	mx23_mem_setup_vddmem();
278 
279 	/*
280 	 * Configure the DRAM registers
281 	 */
282 
283 	/* Clear START and SREFRESH bit from DRAM_CTL8 */
284 	clrbits_le32(MXS_DRAM_BASE + 0x20, (1 << 16) | (1 << 8));
285 
286 	initialize_dram_values();
287 
288 	/* Set START bit in DRAM_CTL8 */
289 	setbits_le32(MXS_DRAM_BASE + 0x20, 1 << 16);
290 
291 	clrbits_le32(MXS_DRAM_BASE + 0x40, 1 << 17);
292 
293 	/* Wait for EMI_STAT bit DRAM_HALTED */
294 	for (;;) {
295 		if (!(readl(MXS_EMI_BASE + 0x10) & (1 << 1)))
296 			break;
297 		early_delay(1000);
298 	}
299 
300 	/* Adjust EMI port priority. */
301 	clrsetbits_le32(0x80020000, 0x1f << 16, 0x2);
302 	early_delay(20000);
303 
304 	setbits_le32(MXS_DRAM_BASE + 0x40, 1 << 19);
305 	setbits_le32(MXS_DRAM_BASE + 0x40, 1 << 11);
306 }
307 #endif
308 
309 #ifdef CONFIG_MX28
310 static void mx28_mem_init(void)
311 {
312 	struct mxs_pinctrl_regs *pinctrl_regs =
313 		(struct mxs_pinctrl_regs *)MXS_PINCTRL_BASE;
314 
315 	debug("SPL: Initialising mx28 SDRAM Controller\n");
316 
317 	/* Set DDR2 mode */
318 	writel(PINCTRL_EMI_DS_CTRL_DDR_MODE_DDR2,
319 		&pinctrl_regs->hw_pinctrl_emi_ds_ctrl_set);
320 
321 	/*
322 	 * Configure the DRAM registers
323 	 */
324 
325 	/* Clear START bit from DRAM_CTL16 */
326 	clrbits_le32(MXS_DRAM_BASE + 0x40, 1);
327 
328 	initialize_dram_values();
329 
330 	/* Clear SREFRESH bit from DRAM_CTL17 */
331 	clrbits_le32(MXS_DRAM_BASE + 0x44, 1);
332 
333 	/* Set START bit in DRAM_CTL16 */
334 	setbits_le32(MXS_DRAM_BASE + 0x40, 1);
335 
336 	/* Wait for bit 20 (DRAM init complete) in DRAM_CTL58 */
337 	while (!(readl(MXS_DRAM_BASE + 0xe8) & (1 << 20)))
338 		;
339 }
340 #endif
341 
342 void mxs_mem_init(void)
343 {
344 	early_delay(11000);
345 
346 	mxs_mem_init_clock();
347 
348 	mxs_mem_setup_vdda();
349 
350 #if defined(CONFIG_MX23)
351 	mx23_mem_init();
352 #elif defined(CONFIG_MX28)
353 	mx28_mem_init();
354 #endif
355 
356 	early_delay(10000);
357 
358 	mxs_mem_setup_cpu_and_hbus();
359 }
360