1 /* 2 * Freescale i.MX28 RAM init 3 * 4 * Copyright (C) 2011 Marek Vasut <marek.vasut@gmail.com> 5 * on behalf of DENX Software Engineering GmbH 6 * 7 * See file CREDITS for list of people who contributed to this 8 * project. 9 * 10 * This program is free software; you can redistribute it and/or 11 * modify it under the terms of the GNU General Public License as 12 * published by the Free Software Foundation; either version 2 of 13 * the License, or (at your option) any later version. 14 * 15 * This program is distributed in the hope that it will be useful, 16 * but WITHOUT ANY WARRANTY; without even the implied warranty of 17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 18 * GNU General Public License for more details. 19 * 20 * You should have received a copy of the GNU General Public License 21 * along with this program; if not, write to the Free Software 22 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 23 * MA 02111-1307 USA 24 */ 25 26 #include <common.h> 27 #include <config.h> 28 #include <asm/io.h> 29 #include <asm/arch/imx-regs.h> 30 #include <asm/arch/sys_proto.h> 31 #include <linux/compiler.h> 32 33 #include "mxs_init.h" 34 35 static uint32_t dram_vals[] = { 36 /* 37 * i.MX28 DDR2 at 200MHz 38 */ 39 #if defined(CONFIG_MX28) 40 0x00000000, 0x00000000, 0x00000000, 0x00000000, 41 0x00000000, 0x00000000, 0x00000000, 0x00000000, 42 0x00000000, 0x00000000, 0x00000000, 0x00000000, 43 0x00000000, 0x00000000, 0x00000000, 0x00000000, 44 0x00000000, 0x00000100, 0x00000000, 0x00000000, 45 0x00000000, 0x00000000, 0x00000000, 0x00000000, 46 0x00000000, 0x00000000, 0x00010101, 0x01010101, 47 0x000f0f01, 0x0f02020a, 0x00000000, 0x00010101, 48 0x00000100, 0x00000100, 0x00000000, 0x00000002, 49 0x01010000, 0x07080403, 0x06005003, 0x0a0000c8, 50 0x02009c40, 0x0002030c, 0x0036a609, 0x031a0612, 51 0x02030202, 0x00c8001c, 0x00000000, 0x00000000, 52 0x00012100, 0xffff0303, 0x00012100, 0xffff0303, 53 0x00012100, 0xffff0303, 0x00012100, 0xffff0303, 54 0x00000003, 0x00000000, 0x00000000, 0x00000000, 55 0x00000000, 0x00000000, 0x00000000, 0x00000000, 56 0x00000000, 0x00000000, 0x00000612, 0x01000F02, 57 0x06120612, 0x00000200, 0x00020007, 0xf4004a27, 58 0xf4004a27, 0xf4004a27, 0xf4004a27, 0x07000300, 59 0x07000300, 0x07400300, 0x07400300, 0x00000005, 60 0x00000000, 0x00000000, 0x01000000, 0x01020408, 61 0x08040201, 0x000f1133, 0x00000000, 0x00001f04, 62 0x00001f04, 0x00001f04, 0x00001f04, 0x00001f04, 63 0x00001f04, 0x00001f04, 0x00001f04, 0x00000000, 64 0x00000000, 0x00000000, 0x00000000, 0x00000000, 65 0x00000000, 0x00000000, 0x00000000, 0x00000000, 66 0x00000000, 0x00000000, 0x00000000, 0x00000000, 67 0x00000000, 0x00000000, 0x00000000, 0x00000000, 68 0x00000000, 0x00000000, 0x00000000, 0x00000000, 69 0x00000000, 0x00000000, 0x00000000, 0x00000000, 70 0x00000000, 0x00000000, 0x00000000, 0x00000000, 71 0x00000000, 0x00000000, 0x00000000, 0x00000000, 72 0x00000000, 0x00000000, 0x00000000, 0x00000000, 73 0x00000000, 0x00000000, 0x00000000, 0x00000000, 74 0x00000000, 0x00000000, 0x00000000, 0x00000000, 75 0x00000000, 0x00000000, 0x00000000, 0x00000000, 76 0x00000000, 0x00000000, 0x00000000, 0x00000000, 77 0x00000000, 0x00000000, 0x00000000, 0x00000000, 78 0x00000000, 0x00000000, 0x00000000, 0x00000000, 79 0x00000000, 0x00000000, 0x00000000, 0x00000000, 80 0x00000000, 0x00000000, 0x00010000, 0x00030404, 81 0x00000003, 0x00000000, 0x00000000, 0x00000000, 82 0x00000000, 0x00000000, 0x00000000, 0x01010000, 83 0x01000000, 0x03030000, 0x00010303, 0x01020202, 84 0x00000000, 0x02040303, 0x21002103, 0x00061200, 85 0x06120612, 0x04420442, 0x04420442, 0x00040004, 86 0x00040004, 0x00000000, 0x00000000, 0x00000000, 87 0x00000000, 0xffffffff 88 89 /* 90 * i.MX23 DDR at 133MHz 91 */ 92 #elif defined(CONFIG_MX23) 93 0x01010001, 0x00010100, 0x01000101, 0x00000001, 94 0x00000101, 0x00000000, 0x00010000, 0x01000001, 95 0x00000000, 0x00000001, 0x07000200, 0x00070202, 96 0x02020000, 0x04040a01, 0x00000201, 0x02040000, 97 0x02000000, 0x19000f08, 0x0d0d0000, 0x02021313, 98 0x02061521, 0x0000000a, 0x00080008, 0x00200020, 99 0x00200020, 0x00200020, 0x000003f7, 0x00000000, 100 0x00000000, 0x00000020, 0x00000020, 0x00c80000, 101 0x000a23cd, 0x000000c8, 0x00006665, 0x00000000, 102 0x00000101, 0x00040001, 0x00000000, 0x00000000, 103 0x00010000 104 #else 105 #error Unsupported memory initialization 106 #endif 107 }; 108 109 __weak void mxs_adjust_memory_params(uint32_t *dram_vals) 110 { 111 } 112 113 #ifdef CONFIG_MX28 114 static void initialize_dram_values(void) 115 { 116 int i; 117 118 mxs_adjust_memory_params(dram_vals); 119 120 for (i = 0; i < ARRAY_SIZE(dram_vals); i++) 121 writel(dram_vals[i], MXS_DRAM_BASE + (4 * i)); 122 } 123 #else 124 static void initialize_dram_values(void) 125 { 126 int i; 127 128 mxs_adjust_memory_params(dram_vals); 129 130 for (i = 0; i < ARRAY_SIZE(dram_vals); i++) { 131 if (i == 8 || i == 27 || i == 28 || i == 35) 132 continue; 133 writel(dram_vals[i], MXS_DRAM_BASE + (4 * i)); 134 } 135 136 /* 137 * Enable tRAS lockout in HW_DRAM_CTL08 ; it must be the last 138 * element to be set 139 */ 140 writel((1 << 24), MXS_DRAM_BASE + (4 * 8)); 141 } 142 #endif 143 144 static void mxs_mem_init_clock(void) 145 { 146 struct mxs_clkctrl_regs *clkctrl_regs = 147 (struct mxs_clkctrl_regs *)MXS_CLKCTRL_BASE; 148 #if defined(CONFIG_MX23) 149 /* Fractional divider for ref_emi is 33 ; 480 * 18 / 33 = 266MHz */ 150 const unsigned char divider = 33; 151 #elif defined(CONFIG_MX28) 152 /* Fractional divider for ref_emi is 21 ; 480 * 18 / 21 = 411MHz */ 153 const unsigned char divider = 21; 154 #endif 155 156 /* Gate EMI clock */ 157 writeb(CLKCTRL_FRAC_CLKGATE, 158 &clkctrl_regs->hw_clkctrl_frac0_set[CLKCTRL_FRAC0_EMI]); 159 160 /* Set fractional divider for ref_emi */ 161 writeb(CLKCTRL_FRAC_CLKGATE | (divider & CLKCTRL_FRAC_FRAC_MASK), 162 &clkctrl_regs->hw_clkctrl_frac0[CLKCTRL_FRAC0_EMI]); 163 164 /* Ungate EMI clock */ 165 writeb(CLKCTRL_FRAC_CLKGATE, 166 &clkctrl_regs->hw_clkctrl_frac0_clr[CLKCTRL_FRAC0_EMI]); 167 168 early_delay(11000); 169 170 /* Set EMI clock divider for EMI clock to 411 / 2 = 205MHz */ 171 writel((2 << CLKCTRL_EMI_DIV_EMI_OFFSET) | 172 (1 << CLKCTRL_EMI_DIV_XTAL_OFFSET), 173 &clkctrl_regs->hw_clkctrl_emi); 174 175 /* Unbypass EMI */ 176 writel(CLKCTRL_CLKSEQ_BYPASS_EMI, 177 &clkctrl_regs->hw_clkctrl_clkseq_clr); 178 179 early_delay(10000); 180 } 181 182 static void mxs_mem_setup_cpu_and_hbus(void) 183 { 184 struct mxs_clkctrl_regs *clkctrl_regs = 185 (struct mxs_clkctrl_regs *)MXS_CLKCTRL_BASE; 186 187 /* Set fractional divider for ref_cpu to 480 * 18 / 19 = 454MHz 188 * and ungate CPU clock */ 189 writeb(19 & CLKCTRL_FRAC_FRAC_MASK, 190 (uint8_t *)&clkctrl_regs->hw_clkctrl_frac0[CLKCTRL_FRAC0_CPU]); 191 192 /* Set CPU bypass */ 193 writel(CLKCTRL_CLKSEQ_BYPASS_CPU, 194 &clkctrl_regs->hw_clkctrl_clkseq_set); 195 196 /* HBUS = 151MHz */ 197 writel(CLKCTRL_HBUS_DIV_MASK, &clkctrl_regs->hw_clkctrl_hbus_set); 198 writel(((~3) << CLKCTRL_HBUS_DIV_OFFSET) & CLKCTRL_HBUS_DIV_MASK, 199 &clkctrl_regs->hw_clkctrl_hbus_clr); 200 201 early_delay(10000); 202 203 /* CPU clock divider = 1 */ 204 clrsetbits_le32(&clkctrl_regs->hw_clkctrl_cpu, 205 CLKCTRL_CPU_DIV_CPU_MASK, 1); 206 207 /* Disable CPU bypass */ 208 writel(CLKCTRL_CLKSEQ_BYPASS_CPU, 209 &clkctrl_regs->hw_clkctrl_clkseq_clr); 210 211 early_delay(15000); 212 } 213 214 static void mxs_mem_setup_vdda(void) 215 { 216 struct mxs_power_regs *power_regs = 217 (struct mxs_power_regs *)MXS_POWER_BASE; 218 219 writel((0xc << POWER_VDDACTRL_TRG_OFFSET) | 220 (0x7 << POWER_VDDACTRL_BO_OFFSET_OFFSET) | 221 POWER_VDDACTRL_LINREG_OFFSET_1STEPS_BELOW, 222 &power_regs->hw_power_vddactrl); 223 } 224 225 uint32_t mxs_mem_get_size(void) 226 { 227 uint32_t sz, da; 228 uint32_t *vt = (uint32_t *)0x20; 229 /* The following is "subs pc, r14, #4", used as return from DABT. */ 230 const uint32_t data_abort_memdetect_handler = 0xe25ef004; 231 232 /* Replace the DABT handler. */ 233 da = vt[4]; 234 vt[4] = data_abort_memdetect_handler; 235 236 sz = get_ram_size((long *)PHYS_SDRAM_1, PHYS_SDRAM_1_SIZE); 237 238 /* Restore the old DABT handler. */ 239 vt[4] = da; 240 241 return sz; 242 } 243 244 #ifdef CONFIG_MX23 245 static void mx23_mem_setup_vddmem(void) 246 { 247 struct mxs_power_regs *power_regs = 248 (struct mxs_power_regs *)MXS_POWER_BASE; 249 250 writel((0x10 << POWER_VDDMEMCTRL_TRG_OFFSET) | 251 POWER_VDDMEMCTRL_ENABLE_ILIMIT | 252 POWER_VDDMEMCTRL_ENABLE_LINREG | 253 POWER_VDDMEMCTRL_PULLDOWN_ACTIVE, 254 &power_regs->hw_power_vddmemctrl); 255 256 early_delay(10000); 257 258 writel((0x10 << POWER_VDDMEMCTRL_TRG_OFFSET) | 259 POWER_VDDMEMCTRL_ENABLE_LINREG, 260 &power_regs->hw_power_vddmemctrl); 261 } 262 263 static void mx23_mem_init(void) 264 { 265 /* 266 * Reset/ungate the EMI block. This is essential, otherwise the system 267 * suffers from memory instability. This thing is mx23 specific and is 268 * no longer present on mx28. 269 */ 270 mxs_reset_block((struct mxs_register_32 *)MXS_EMI_BASE); 271 272 mx23_mem_setup_vddmem(); 273 274 /* 275 * Configure the DRAM registers 276 */ 277 278 /* Clear START and SREFRESH bit from DRAM_CTL8 */ 279 clrbits_le32(MXS_DRAM_BASE + 0x20, (1 << 16) | (1 << 8)); 280 281 initialize_dram_values(); 282 283 /* Set START bit in DRAM_CTL8 */ 284 setbits_le32(MXS_DRAM_BASE + 0x20, 1 << 16); 285 286 clrbits_le32(MXS_DRAM_BASE + 0x40, 1 << 17); 287 early_delay(20000); 288 289 /* Adjust EMI port priority. */ 290 clrsetbits_le32(0x80020000, 0x1f << 16, 0x2); 291 early_delay(20000); 292 293 setbits_le32(MXS_DRAM_BASE + 0x40, 1 << 19); 294 setbits_le32(MXS_DRAM_BASE + 0x40, 1 << 11); 295 } 296 #endif 297 298 #ifdef CONFIG_MX28 299 static void mx28_mem_init(void) 300 { 301 struct mxs_pinctrl_regs *pinctrl_regs = 302 (struct mxs_pinctrl_regs *)MXS_PINCTRL_BASE; 303 304 /* Set DDR2 mode */ 305 writel(PINCTRL_EMI_DS_CTRL_DDR_MODE_DDR2, 306 &pinctrl_regs->hw_pinctrl_emi_ds_ctrl_set); 307 308 /* 309 * Configure the DRAM registers 310 */ 311 312 /* Clear START bit from DRAM_CTL16 */ 313 clrbits_le32(MXS_DRAM_BASE + 0x40, 1); 314 315 initialize_dram_values(); 316 317 /* Clear SREFRESH bit from DRAM_CTL17 */ 318 clrbits_le32(MXS_DRAM_BASE + 0x44, 1); 319 320 /* Set START bit in DRAM_CTL16 */ 321 setbits_le32(MXS_DRAM_BASE + 0x40, 1); 322 323 /* Wait for bit 20 (DRAM init complete) in DRAM_CTL58 */ 324 while (!(readl(MXS_DRAM_BASE + 0xe8) & (1 << 20))) 325 ; 326 } 327 #endif 328 329 void mxs_mem_init(void) 330 { 331 early_delay(11000); 332 333 mxs_mem_init_clock(); 334 335 mxs_mem_setup_vdda(); 336 337 #if defined(CONFIG_MX23) 338 mx23_mem_init(); 339 #elif defined(CONFIG_MX28) 340 mx28_mem_init(); 341 #endif 342 343 early_delay(10000); 344 345 mxs_mem_setup_cpu_and_hbus(); 346 } 347