1 /*
2  * Freescale i.MX28 Battery measurement init
3  *
4  * Copyright (C) 2011 Marek Vasut <marek.vasut@gmail.com>
5  * on behalf of DENX Software Engineering GmbH
6  *
7  * SPDX-License-Identifier:	GPL-2.0+
8  */
9 
10 #include <common.h>
11 #include <config.h>
12 #include <asm/io.h>
13 #include <asm/arch/imx-regs.h>
14 
15 #include "mxs_init.h"
16 
17 void mxs_lradc_init(void)
18 {
19 	struct mxs_lradc_regs *regs = (struct mxs_lradc_regs *)MXS_LRADC_BASE;
20 
21 	writel(LRADC_CTRL0_SFTRST, &regs->hw_lradc_ctrl0_clr);
22 	writel(LRADC_CTRL0_CLKGATE, &regs->hw_lradc_ctrl0_clr);
23 	writel(LRADC_CTRL0_ONCHIP_GROUNDREF, &regs->hw_lradc_ctrl0_clr);
24 
25 	clrsetbits_le32(&regs->hw_lradc_ctrl3,
26 			LRADC_CTRL3_CYCLE_TIME_MASK,
27 			LRADC_CTRL3_CYCLE_TIME_6MHZ);
28 
29 	clrsetbits_le32(&regs->hw_lradc_ctrl4,
30 			LRADC_CTRL4_LRADC7SELECT_MASK |
31 			LRADC_CTRL4_LRADC6SELECT_MASK,
32 			LRADC_CTRL4_LRADC7SELECT_CHANNEL7 |
33 			LRADC_CTRL4_LRADC6SELECT_CHANNEL10);
34 }
35 
36 void mxs_lradc_enable_batt_measurement(void)
37 {
38 	struct mxs_lradc_regs *regs = (struct mxs_lradc_regs *)MXS_LRADC_BASE;
39 
40 	/* Check if the channel is present at all. */
41 	if (!(readl(&regs->hw_lradc_status) & LRADC_STATUS_CHANNEL7_PRESENT))
42 		return;
43 
44 	writel(LRADC_CTRL1_LRADC7_IRQ_EN, &regs->hw_lradc_ctrl1_clr);
45 	writel(LRADC_CTRL1_LRADC7_IRQ, &regs->hw_lradc_ctrl1_clr);
46 
47 	clrsetbits_le32(&regs->hw_lradc_conversion,
48 			LRADC_CONVERSION_SCALE_FACTOR_MASK,
49 			LRADC_CONVERSION_SCALE_FACTOR_LI_ION);
50 	writel(LRADC_CONVERSION_AUTOMATIC, &regs->hw_lradc_conversion_set);
51 
52 	/* Configure the channel. */
53 	writel((1 << 7) << LRADC_CTRL2_DIVIDE_BY_TWO_OFFSET,
54 		&regs->hw_lradc_ctrl2_clr);
55 	writel(0xffffffff, &regs->hw_lradc_ch7_clr);
56 	clrbits_le32(&regs->hw_lradc_ch7, LRADC_CH_NUM_SAMPLES_MASK);
57 	writel(LRADC_CH_ACCUMULATE, &regs->hw_lradc_ch7_clr);
58 
59 	/* Schedule the channel. */
60 	writel(1 << 7, &regs->hw_lradc_ctrl0_set);
61 
62 	/* Start the channel sampling. */
63 	writel(((1 << 7) << LRADC_DELAY_TRIGGER_LRADCS_OFFSET) |
64 		((1 << 3) << LRADC_DELAY_TRIGGER_DELAYS_OFFSET) |
65 		100, &regs->hw_lradc_delay3);
66 
67 	writel(0xffffffff, &regs->hw_lradc_ch7_clr);
68 
69 	writel(LRADC_DELAY_KICK, &regs->hw_lradc_delay3_set);
70 }
71