1 /* 2 * Freescale i.MX28 Battery measurement init 3 * 4 * Copyright (C) 2011 Marek Vasut <marek.vasut@gmail.com> 5 * on behalf of DENX Software Engineering GmbH 6 * 7 * SPDX-License-Identifier: GPL-2.0+ 8 */ 9 10 #include <common.h> 11 #include <config.h> 12 #include <asm/io.h> 13 #include <asm/arch/imx-regs.h> 14 15 #include "mxs_init.h" 16 17 void mxs_lradc_init(void) 18 { 19 struct mxs_lradc_regs *regs = (struct mxs_lradc_regs *)MXS_LRADC_BASE; 20 21 debug("SPL: Initialisating LRADC\n"); 22 23 writel(LRADC_CTRL0_SFTRST, ®s->hw_lradc_ctrl0_clr); 24 writel(LRADC_CTRL0_CLKGATE, ®s->hw_lradc_ctrl0_clr); 25 writel(LRADC_CTRL0_ONCHIP_GROUNDREF, ®s->hw_lradc_ctrl0_clr); 26 27 clrsetbits_le32(®s->hw_lradc_ctrl3, 28 LRADC_CTRL3_CYCLE_TIME_MASK, 29 LRADC_CTRL3_CYCLE_TIME_6MHZ); 30 31 clrsetbits_le32(®s->hw_lradc_ctrl4, 32 LRADC_CTRL4_LRADC7SELECT_MASK | 33 LRADC_CTRL4_LRADC6SELECT_MASK, 34 LRADC_CTRL4_LRADC7SELECT_CHANNEL7 | 35 LRADC_CTRL4_LRADC6SELECT_CHANNEL10); 36 } 37 38 void mxs_lradc_enable_batt_measurement(void) 39 { 40 struct mxs_lradc_regs *regs = (struct mxs_lradc_regs *)MXS_LRADC_BASE; 41 42 debug("SPL: Enabling LRADC battery measurement\n"); 43 44 /* Check if the channel is present at all. */ 45 if (!(readl(®s->hw_lradc_status) & LRADC_STATUS_CHANNEL7_PRESENT)) { 46 debug("SPL: LRADC channel 7 is not present - aborting\n"); 47 return; 48 } 49 50 debug("SPL: LRADC channel 7 is present - configuring\n"); 51 52 writel(LRADC_CTRL1_LRADC7_IRQ_EN, ®s->hw_lradc_ctrl1_clr); 53 writel(LRADC_CTRL1_LRADC7_IRQ, ®s->hw_lradc_ctrl1_clr); 54 55 clrsetbits_le32(®s->hw_lradc_conversion, 56 LRADC_CONVERSION_SCALE_FACTOR_MASK, 57 LRADC_CONVERSION_SCALE_FACTOR_LI_ION); 58 writel(LRADC_CONVERSION_AUTOMATIC, ®s->hw_lradc_conversion_set); 59 60 /* Configure the channel. */ 61 writel((1 << 7) << LRADC_CTRL2_DIVIDE_BY_TWO_OFFSET, 62 ®s->hw_lradc_ctrl2_clr); 63 writel(0xffffffff, ®s->hw_lradc_ch7_clr); 64 clrbits_le32(®s->hw_lradc_ch7, LRADC_CH_NUM_SAMPLES_MASK); 65 writel(LRADC_CH_ACCUMULATE, ®s->hw_lradc_ch7_clr); 66 67 /* Schedule the channel. */ 68 writel(1 << 7, ®s->hw_lradc_ctrl0_set); 69 70 /* Start the channel sampling. */ 71 writel(((1 << 7) << LRADC_DELAY_TRIGGER_LRADCS_OFFSET) | 72 ((1 << 3) << LRADC_DELAY_TRIGGER_DELAYS_OFFSET) | 73 100, ®s->hw_lradc_delay3); 74 75 writel(0xffffffff, ®s->hw_lradc_ch7_clr); 76 writel(LRADC_DELAY_KICK, ®s->hw_lradc_delay3_set); 77 78 debug("SPL: LRADC channel 7 configuration complete\n"); 79 } 80