1 // SPDX-License-Identifier: GPL-2.0+ 2 /* 3 * Freescale i.MX23/i.MX28 common code 4 * 5 * Copyright (C) 2011 Marek Vasut <marek.vasut@gmail.com> 6 * on behalf of DENX Software Engineering GmbH 7 * 8 * Based on code from LTIB: 9 * Copyright (C) 2010 Freescale Semiconductor, Inc. 10 */ 11 12 #include <common.h> 13 #include <linux/errno.h> 14 #include <asm/io.h> 15 #include <asm/arch/clock.h> 16 #include <asm/mach-imx/dma.h> 17 #include <asm/arch/gpio.h> 18 #include <asm/arch/iomux.h> 19 #include <asm/arch/imx-regs.h> 20 #include <asm/arch/sys_proto.h> 21 #include <linux/compiler.h> 22 23 DECLARE_GLOBAL_DATA_PTR; 24 25 /* Lowlevel init isn't used on i.MX28, so just have a dummy here */ 26 __weak void lowlevel_init(void) {} 27 28 void reset_cpu(ulong ignored) __attribute__((noreturn)); 29 30 void reset_cpu(ulong ignored) 31 { 32 struct mxs_rtc_regs *rtc_regs = 33 (struct mxs_rtc_regs *)MXS_RTC_BASE; 34 struct mxs_lcdif_regs *lcdif_regs = 35 (struct mxs_lcdif_regs *)MXS_LCDIF_BASE; 36 37 /* 38 * Shut down the LCD controller as it interferes with BootROM boot mode 39 * pads sampling. 40 */ 41 writel(LCDIF_CTRL_RUN, &lcdif_regs->hw_lcdif_ctrl_clr); 42 43 /* Wait 1 uS before doing the actual watchdog reset */ 44 writel(1, &rtc_regs->hw_rtc_watchdog); 45 writel(RTC_CTRL_WATCHDOGEN, &rtc_regs->hw_rtc_ctrl_set); 46 47 /* Endless loop, reset will exit from here */ 48 for (;;) 49 ; 50 } 51 52 void enable_caches(void) 53 { 54 #ifndef CONFIG_SYS_ICACHE_OFF 55 icache_enable(); 56 #endif 57 #ifndef CONFIG_SYS_DCACHE_OFF 58 dcache_enable(); 59 #endif 60 } 61 62 /* 63 * This function will craft a jumptable at 0x0 which will redirect interrupt 64 * vectoring to proper location of U-Boot in RAM. 65 * 66 * The structure of the jumptable will be as follows: 67 * ldr pc, [pc, #0x18] ..... for each vector, thus repeated 8 times 68 * <destination address> ... for each previous ldr, thus also repeated 8 times 69 * 70 * The "ldr pc, [pc, #0x18]" instruction above loads address from memory at 71 * offset 0x18 from current value of PC register. Note that PC is already 72 * incremented by 4 when computing the offset, so the effective offset is 73 * actually 0x20, this the associated <destination address>. Loading the PC 74 * register with an address performs a jump to that address. 75 */ 76 void mx28_fixup_vt(uint32_t start_addr) 77 { 78 /* ldr pc, [pc, #0x18] */ 79 const uint32_t ldr_pc = 0xe59ff018; 80 /* Jumptable location is 0x0 */ 81 uint32_t *vt = (uint32_t *)0x0; 82 int i; 83 84 for (i = 0; i < 8; i++) { 85 /* cppcheck-suppress nullPointer */ 86 vt[i] = ldr_pc; 87 /* cppcheck-suppress nullPointer */ 88 vt[i + 8] = start_addr + (4 * i); 89 } 90 } 91 92 #ifdef CONFIG_ARCH_MISC_INIT 93 int arch_misc_init(void) 94 { 95 mx28_fixup_vt(gd->relocaddr); 96 return 0; 97 } 98 #endif 99 100 int arch_cpu_init(void) 101 { 102 struct mxs_clkctrl_regs *clkctrl_regs = 103 (struct mxs_clkctrl_regs *)MXS_CLKCTRL_BASE; 104 extern uint32_t _start; 105 106 mx28_fixup_vt((uint32_t)&_start); 107 108 /* 109 * Enable NAND clock 110 */ 111 /* Clear bypass bit */ 112 writel(CLKCTRL_CLKSEQ_BYPASS_GPMI, 113 &clkctrl_regs->hw_clkctrl_clkseq_set); 114 115 /* Set GPMI clock to ref_gpmi / 12 */ 116 clrsetbits_le32(&clkctrl_regs->hw_clkctrl_gpmi, 117 CLKCTRL_GPMI_CLKGATE | CLKCTRL_GPMI_DIV_MASK, 1); 118 119 udelay(1000); 120 121 /* 122 * Configure GPIO unit 123 */ 124 mxs_gpio_init(); 125 126 #ifdef CONFIG_APBH_DMA 127 /* Start APBH DMA */ 128 mxs_dma_init(); 129 #endif 130 131 return 0; 132 } 133 134 u32 get_cpu_rev(void) 135 { 136 struct mxs_digctl_regs *digctl_regs = 137 (struct mxs_digctl_regs *)MXS_DIGCTL_BASE; 138 uint8_t rev = readl(&digctl_regs->hw_digctl_chipid) & 0x000000FF; 139 140 switch (readl(&digctl_regs->hw_digctl_chipid) & HW_DIGCTL_CHIPID_MASK) { 141 case HW_DIGCTL_CHIPID_MX23: 142 switch (rev) { 143 case 0x0: 144 case 0x1: 145 case 0x2: 146 case 0x3: 147 case 0x4: 148 return (MXC_CPU_MX23 << 12) | (rev + 0x10); 149 default: 150 return 0; 151 } 152 case HW_DIGCTL_CHIPID_MX28: 153 switch (rev) { 154 case 0x1: 155 return (MXC_CPU_MX28 << 12) | 0x12; 156 default: 157 return 0; 158 } 159 default: 160 return 0; 161 } 162 } 163 164 #if defined(CONFIG_DISPLAY_CPUINFO) 165 const char *get_imx_type(u32 imxtype) 166 { 167 switch (imxtype) { 168 case MXC_CPU_MX23: 169 return "23"; 170 case MXC_CPU_MX28: 171 return "28"; 172 default: 173 return "??"; 174 } 175 } 176 177 int print_cpuinfo(void) 178 { 179 u32 cpurev; 180 struct mxs_spl_data *data = MXS_SPL_DATA; 181 182 cpurev = get_cpu_rev(); 183 printf("CPU: Freescale i.MX%s rev%d.%d at %d MHz\n", 184 get_imx_type((cpurev & 0xFF000) >> 12), 185 (cpurev & 0x000F0) >> 4, 186 (cpurev & 0x0000F) >> 0, 187 mxc_get_clock(MXC_ARM_CLK) / 1000000); 188 printf("BOOT: %s\n", mxs_boot_modes[data->boot_mode_idx].mode); 189 return 0; 190 } 191 #endif 192 193 int do_mx28_showclocks(cmd_tbl_t *cmdtp, int flag, int argc, char *const argv[]) 194 { 195 printf("CPU: %3d MHz\n", mxc_get_clock(MXC_ARM_CLK) / 1000000); 196 printf("BUS: %3d MHz\n", mxc_get_clock(MXC_AHB_CLK) / 1000000); 197 printf("EMI: %3d MHz\n", mxc_get_clock(MXC_EMI_CLK)); 198 printf("GPMI: %3d MHz\n", mxc_get_clock(MXC_GPMI_CLK) / 1000000); 199 return 0; 200 } 201 202 /* 203 * Initializes on-chip ethernet controllers. 204 */ 205 #if defined(CONFIG_MX28) && defined(CONFIG_CMD_NET) 206 int cpu_eth_init(bd_t *bis) 207 { 208 struct mxs_clkctrl_regs *clkctrl_regs = 209 (struct mxs_clkctrl_regs *)MXS_CLKCTRL_BASE; 210 211 /* Turn on ENET clocks */ 212 clrbits_le32(&clkctrl_regs->hw_clkctrl_enet, 213 CLKCTRL_ENET_SLEEP | CLKCTRL_ENET_DISABLE); 214 215 /* Set up ENET PLL for 50 MHz */ 216 /* Power on ENET PLL */ 217 writel(CLKCTRL_PLL2CTRL0_POWER, 218 &clkctrl_regs->hw_clkctrl_pll2ctrl0_set); 219 220 udelay(10); 221 222 /* Gate on ENET PLL */ 223 writel(CLKCTRL_PLL2CTRL0_CLKGATE, 224 &clkctrl_regs->hw_clkctrl_pll2ctrl0_clr); 225 226 /* Enable pad output */ 227 setbits_le32(&clkctrl_regs->hw_clkctrl_enet, CLKCTRL_ENET_CLK_OUT_EN); 228 229 return 0; 230 } 231 #endif 232 233 __weak void mx28_adjust_mac(int dev_id, unsigned char *mac) 234 { 235 mac[0] = 0x00; 236 mac[1] = 0x04; /* Use FSL vendor MAC address by default */ 237 238 if (dev_id == 1) /* Let MAC1 be MAC0 + 1 by default */ 239 mac[5] += 1; 240 } 241 242 #ifdef CONFIG_MX28_FEC_MAC_IN_OCOTP 243 244 #define MXS_OCOTP_MAX_TIMEOUT 1000000 245 void imx_get_mac_from_fuse(int dev_id, unsigned char *mac) 246 { 247 struct mxs_ocotp_regs *ocotp_regs = 248 (struct mxs_ocotp_regs *)MXS_OCOTP_BASE; 249 uint32_t data; 250 251 memset(mac, 0, 6); 252 253 writel(OCOTP_CTRL_RD_BANK_OPEN, &ocotp_regs->hw_ocotp_ctrl_set); 254 255 if (mxs_wait_mask_clr(&ocotp_regs->hw_ocotp_ctrl_reg, OCOTP_CTRL_BUSY, 256 MXS_OCOTP_MAX_TIMEOUT)) { 257 printf("MXS FEC: Can't get MAC from OCOTP\n"); 258 return; 259 } 260 261 data = readl(&ocotp_regs->hw_ocotp_cust0); 262 263 mac[2] = (data >> 24) & 0xff; 264 mac[3] = (data >> 16) & 0xff; 265 mac[4] = (data >> 8) & 0xff; 266 mac[5] = data & 0xff; 267 mx28_adjust_mac(dev_id, mac); 268 } 269 #else 270 void imx_get_mac_from_fuse(int dev_id, unsigned char *mac) 271 { 272 memset(mac, 0, 6); 273 } 274 #endif 275 276 int mxs_dram_init(void) 277 { 278 struct mxs_spl_data *data = MXS_SPL_DATA; 279 280 if (data->mem_dram_size == 0) { 281 printf("MXS:\n" 282 "Error, the RAM size passed up from SPL is 0!\n"); 283 hang(); 284 } 285 286 gd->ram_size = data->mem_dram_size; 287 return 0; 288 } 289 290 U_BOOT_CMD( 291 clocks, CONFIG_SYS_MAXARGS, 1, do_mx28_showclocks, 292 "display clocks", 293 "" 294 ); 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