1 /* 2 * Freescale i.MX23/i.MX28 common code 3 * 4 * Copyright (C) 2011 Marek Vasut <marek.vasut@gmail.com> 5 * on behalf of DENX Software Engineering GmbH 6 * 7 * Based on code from LTIB: 8 * Copyright (C) 2010 Freescale Semiconductor, Inc. 9 * 10 * See file CREDITS for list of people who contributed to this 11 * project. 12 * 13 * This program is free software; you can redistribute it and/or 14 * modify it under the terms of the GNU General Public License as 15 * published by the Free Software Foundation; either version 2 of 16 * the License, or (at your option) any later version. 17 * 18 * This program is distributed in the hope that it will be useful, 19 * but WITHOUT ANY WARRANTY; without even the implied warranty of 20 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 21 * GNU General Public License for more details. 22 * 23 * You should have received a copy of the GNU General Public License 24 * along with this program; if not, write to the Free Software 25 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 26 * MA 02111-1307 USA 27 */ 28 29 #include <common.h> 30 #include <asm/errno.h> 31 #include <asm/io.h> 32 #include <asm/arch/clock.h> 33 #include <asm/imx-common/dma.h> 34 #include <asm/arch/gpio.h> 35 #include <asm/arch/iomux.h> 36 #include <asm/arch/imx-regs.h> 37 #include <asm/arch/sys_proto.h> 38 #include <linux/compiler.h> 39 40 DECLARE_GLOBAL_DATA_PTR; 41 42 /* Lowlevel init isn't used on i.MX28, so just have a dummy here */ 43 inline void lowlevel_init(void) {} 44 45 void reset_cpu(ulong ignored) __attribute__((noreturn)); 46 47 void reset_cpu(ulong ignored) 48 { 49 struct mxs_rtc_regs *rtc_regs = 50 (struct mxs_rtc_regs *)MXS_RTC_BASE; 51 struct mxs_lcdif_regs *lcdif_regs = 52 (struct mxs_lcdif_regs *)MXS_LCDIF_BASE; 53 54 /* 55 * Shut down the LCD controller as it interferes with BootROM boot mode 56 * pads sampling. 57 */ 58 writel(LCDIF_CTRL_RUN, &lcdif_regs->hw_lcdif_ctrl_clr); 59 60 /* Wait 1 uS before doing the actual watchdog reset */ 61 writel(1, &rtc_regs->hw_rtc_watchdog); 62 writel(RTC_CTRL_WATCHDOGEN, &rtc_regs->hw_rtc_ctrl_set); 63 64 /* Endless loop, reset will exit from here */ 65 for (;;) 66 ; 67 } 68 69 void enable_caches(void) 70 { 71 #ifndef CONFIG_SYS_ICACHE_OFF 72 icache_enable(); 73 #endif 74 #ifndef CONFIG_SYS_DCACHE_OFF 75 dcache_enable(); 76 #endif 77 } 78 79 void mx28_fixup_vt(uint32_t start_addr) 80 { 81 uint32_t *vt = (uint32_t *)0x20; 82 int i; 83 84 for (i = 0; i < 8; i++) 85 vt[i] = start_addr + (4 * i); 86 } 87 88 #ifdef CONFIG_ARCH_MISC_INIT 89 int arch_misc_init(void) 90 { 91 mx28_fixup_vt(gd->relocaddr); 92 return 0; 93 } 94 #endif 95 96 int arch_cpu_init(void) 97 { 98 struct mxs_clkctrl_regs *clkctrl_regs = 99 (struct mxs_clkctrl_regs *)MXS_CLKCTRL_BASE; 100 extern uint32_t _start; 101 102 mx28_fixup_vt((uint32_t)&_start); 103 104 /* 105 * Enable NAND clock 106 */ 107 /* Clear bypass bit */ 108 writel(CLKCTRL_CLKSEQ_BYPASS_GPMI, 109 &clkctrl_regs->hw_clkctrl_clkseq_set); 110 111 /* Set GPMI clock to ref_gpmi / 12 */ 112 clrsetbits_le32(&clkctrl_regs->hw_clkctrl_gpmi, 113 CLKCTRL_GPMI_CLKGATE | CLKCTRL_GPMI_DIV_MASK, 1); 114 115 udelay(1000); 116 117 /* 118 * Configure GPIO unit 119 */ 120 mxs_gpio_init(); 121 122 #ifdef CONFIG_APBH_DMA 123 /* Start APBH DMA */ 124 mxs_dma_init(); 125 #endif 126 127 return 0; 128 } 129 130 #if defined(CONFIG_DISPLAY_CPUINFO) 131 static const char *get_cpu_type(void) 132 { 133 struct mxs_digctl_regs *digctl_regs = 134 (struct mxs_digctl_regs *)MXS_DIGCTL_BASE; 135 136 switch (readl(&digctl_regs->hw_digctl_chipid) & HW_DIGCTL_CHIPID_MASK) { 137 case HW_DIGCTL_CHIPID_MX23: 138 return "23"; 139 case HW_DIGCTL_CHIPID_MX28: 140 return "28"; 141 default: 142 return "??"; 143 } 144 } 145 146 static const char *get_cpu_rev(void) 147 { 148 struct mxs_digctl_regs *digctl_regs = 149 (struct mxs_digctl_regs *)MXS_DIGCTL_BASE; 150 uint8_t rev = readl(&digctl_regs->hw_digctl_chipid) & 0x000000FF; 151 152 switch (readl(&digctl_regs->hw_digctl_chipid) & HW_DIGCTL_CHIPID_MASK) { 153 case HW_DIGCTL_CHIPID_MX23: 154 switch (rev) { 155 case 0x0: 156 return "1.0"; 157 case 0x1: 158 return "1.1"; 159 case 0x2: 160 return "1.2"; 161 case 0x3: 162 return "1.3"; 163 case 0x4: 164 return "1.4"; 165 default: 166 return "??"; 167 } 168 case HW_DIGCTL_CHIPID_MX28: 169 switch (rev) { 170 case 0x1: 171 return "1.2"; 172 default: 173 return "??"; 174 } 175 default: 176 return "??"; 177 } 178 } 179 180 int print_cpuinfo(void) 181 { 182 struct mxs_spl_data *data = (struct mxs_spl_data *) 183 ((CONFIG_SYS_TEXT_BASE - sizeof(struct mxs_spl_data)) & ~0xf); 184 185 printf("CPU: Freescale i.MX%s rev%s at %d MHz\n", 186 get_cpu_type(), 187 get_cpu_rev(), 188 mxc_get_clock(MXC_ARM_CLK) / 1000000); 189 printf("BOOT: %s\n", mxs_boot_modes[data->boot_mode_idx].mode); 190 return 0; 191 } 192 #endif 193 194 int do_mx28_showclocks(cmd_tbl_t *cmdtp, int flag, int argc, char *const argv[]) 195 { 196 printf("CPU: %3d MHz\n", mxc_get_clock(MXC_ARM_CLK) / 1000000); 197 printf("BUS: %3d MHz\n", mxc_get_clock(MXC_AHB_CLK) / 1000000); 198 printf("EMI: %3d MHz\n", mxc_get_clock(MXC_EMI_CLK)); 199 printf("GPMI: %3d MHz\n", mxc_get_clock(MXC_GPMI_CLK) / 1000000); 200 return 0; 201 } 202 203 /* 204 * Initializes on-chip ethernet controllers. 205 */ 206 #if defined(CONFIG_MX28) && defined(CONFIG_CMD_NET) 207 int cpu_eth_init(bd_t *bis) 208 { 209 struct mxs_clkctrl_regs *clkctrl_regs = 210 (struct mxs_clkctrl_regs *)MXS_CLKCTRL_BASE; 211 212 /* Turn on ENET clocks */ 213 clrbits_le32(&clkctrl_regs->hw_clkctrl_enet, 214 CLKCTRL_ENET_SLEEP | CLKCTRL_ENET_DISABLE); 215 216 /* Set up ENET PLL for 50 MHz */ 217 /* Power on ENET PLL */ 218 writel(CLKCTRL_PLL2CTRL0_POWER, 219 &clkctrl_regs->hw_clkctrl_pll2ctrl0_set); 220 221 udelay(10); 222 223 /* Gate on ENET PLL */ 224 writel(CLKCTRL_PLL2CTRL0_CLKGATE, 225 &clkctrl_regs->hw_clkctrl_pll2ctrl0_clr); 226 227 /* Enable pad output */ 228 setbits_le32(&clkctrl_regs->hw_clkctrl_enet, CLKCTRL_ENET_CLK_OUT_EN); 229 230 return 0; 231 } 232 #endif 233 234 __weak void mx28_adjust_mac(int dev_id, unsigned char *mac) 235 { 236 mac[0] = 0x00; 237 mac[1] = 0x04; /* Use FSL vendor MAC address by default */ 238 239 if (dev_id == 1) /* Let MAC1 be MAC0 + 1 by default */ 240 mac[5] += 1; 241 } 242 243 #ifdef CONFIG_MX28_FEC_MAC_IN_OCOTP 244 245 #define MXS_OCOTP_MAX_TIMEOUT 1000000 246 void imx_get_mac_from_fuse(int dev_id, unsigned char *mac) 247 { 248 struct mxs_ocotp_regs *ocotp_regs = 249 (struct mxs_ocotp_regs *)MXS_OCOTP_BASE; 250 uint32_t data; 251 252 memset(mac, 0, 6); 253 254 writel(OCOTP_CTRL_RD_BANK_OPEN, &ocotp_regs->hw_ocotp_ctrl_set); 255 256 if (mxs_wait_mask_clr(&ocotp_regs->hw_ocotp_ctrl_reg, OCOTP_CTRL_BUSY, 257 MXS_OCOTP_MAX_TIMEOUT)) { 258 printf("MXS FEC: Can't get MAC from OCOTP\n"); 259 return; 260 } 261 262 data = readl(&ocotp_regs->hw_ocotp_cust0); 263 264 mac[2] = (data >> 24) & 0xff; 265 mac[3] = (data >> 16) & 0xff; 266 mac[4] = (data >> 8) & 0xff; 267 mac[5] = data & 0xff; 268 mx28_adjust_mac(dev_id, mac); 269 } 270 #else 271 void imx_get_mac_from_fuse(int dev_id, unsigned char *mac) 272 { 273 memset(mac, 0, 6); 274 } 275 #endif 276 277 int mxs_dram_init(void) 278 { 279 struct mxs_spl_data *data = (struct mxs_spl_data *) 280 ((CONFIG_SYS_TEXT_BASE - sizeof(struct mxs_spl_data)) & ~0xf); 281 282 if (data->mem_dram_size == 0) { 283 printf("MXS:\n" 284 "Error, the RAM size passed up from SPL is 0!\n"); 285 hang(); 286 } 287 288 gd->ram_size = data->mem_dram_size; 289 return 0; 290 } 291 292 U_BOOT_CMD( 293 clocks, CONFIG_SYS_MAXARGS, 1, do_mx28_showclocks, 294 "display clocks", 295 "" 296 ); 297