xref: /openbmc/u-boot/arch/arm/cpu/arm926ejs/mx27/timer.c (revision 63495ad7)
1 /*
2  * (C) Copyright 2002
3  * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
4  * Marius Groeger <mgroeger@sysgo.de>
5  *
6  * (C) Copyright 2002
7  * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
8  * Alex Zuepke <azu@sysgo.de>
9  *
10  * (C) Copyright 2002
11  * Gary Jennejohn, DENX Software Engineering, <gj@denx.de>
12  *
13  * (C) Copyright 2009
14  * Ilya Yanok, Emcraft Systems Ltd, <yanok@emcraft.com>
15  *
16  * See file CREDITS for list of people who contributed to this
17  * project.
18  *
19  * This program is free software; you can redistribute it and/or
20  * modify it under the terms of the GNU General Public License as
21  * published by the Free Software Foundation; either version 2 of
22  * the License, or (at your option) any later version.
23  *
24  * This program is distributed in the hope that it will be useful,
25  * but WITHOUT ANY WARRANTY; without even the implied warranty of
26  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
27  * GNU General Public License for more details.
28  *
29  * You should have received a copy of the GNU General Public License
30  * along with this program; if not, write to the Free Software
31  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
32  * MA 02111-1307 USA
33  */
34 
35 #include <common.h>
36 #include <div64.h>
37 #include <asm/io.h>
38 #include <asm/arch/imx-regs.h>
39 
40 /* General purpose timers bitfields */
41 #define GPTCR_SWR		(1 << 15)	/* Software reset	*/
42 #define GPTCR_FRR		(1 << 8)	/* Freerun / restart	*/
43 #define GPTCR_CLKSOURCE_32	(4 << 1)	/* Clock source		*/
44 #define GPTCR_TEN		1		/* Timer enable		*/
45 
46 DECLARE_GLOBAL_DATA_PTR;
47 
48 #define timestamp	(gd->arch.tbl)
49 #define lastinc		(gd->arch.lastinc)
50 
51 /*
52  * "time" is measured in 1 / CONFIG_SYS_HZ seconds,
53  * "tick" is internal timer period
54  */
55 #ifdef CONFIG_MX27_TIMER_HIGH_PRECISION
56 /* ~0.4% error - measured with stop-watch on 100s boot-delay */
57 static inline unsigned long long tick_to_time(unsigned long long tick)
58 {
59 	tick *= CONFIG_SYS_HZ;
60 	do_div(tick, CONFIG_MX27_CLK32);
61 	return tick;
62 }
63 
64 static inline unsigned long long time_to_tick(unsigned long long time)
65 {
66 	time *= CONFIG_MX27_CLK32;
67 	do_div(time, CONFIG_SYS_HZ);
68 	return time;
69 }
70 
71 static inline unsigned long long us_to_tick(unsigned long long us)
72 {
73 	us = us * CONFIG_MX27_CLK32 + 999999;
74 	do_div(us, 1000000);
75 	return us;
76 }
77 #else
78 /* ~2% error */
79 #define TICK_PER_TIME	((CONFIG_MX27_CLK32 + CONFIG_SYS_HZ / 2) / \
80 		CONFIG_SYS_HZ)
81 #define US_PER_TICK	(1000000 / CONFIG_MX27_CLK32)
82 
83 static inline unsigned long long tick_to_time(unsigned long long tick)
84 {
85 	do_div(tick, TICK_PER_TIME);
86 	return tick;
87 }
88 
89 static inline unsigned long long time_to_tick(unsigned long long time)
90 {
91 	return time * TICK_PER_TIME;
92 }
93 
94 static inline unsigned long long us_to_tick(unsigned long long us)
95 {
96 	us += US_PER_TICK - 1;
97 	do_div(us, US_PER_TICK);
98 	return us;
99 }
100 #endif
101 
102 /* nothing really to do with interrupts, just starts up a counter. */
103 /* The 32768Hz 32-bit timer overruns in 131072 seconds */
104 int timer_init(void)
105 {
106 	int i;
107 	struct gpt_regs *regs = (struct gpt_regs *)IMX_TIM1_BASE;
108 	struct pll_regs *pll = (struct pll_regs *)IMX_PLL_BASE;
109 
110 	/* setup GP Timer 1 */
111 	writel(GPTCR_SWR, &regs->gpt_tctl);
112 
113 	writel(readl(&pll->pccr0) | PCCR0_GPT1_EN, &pll->pccr0);
114 	writel(readl(&pll->pccr1) | PCCR1_PERCLK1_EN, &pll->pccr1);
115 
116 	for (i = 0; i < 100; i++)
117 		writel(0, &regs->gpt_tctl); /* We have no udelay by now */
118 	writel(0, &regs->gpt_tprer); /* 32Khz */
119 	/* Freerun Mode, PERCLK1 input */
120 	writel(readl(&regs->gpt_tctl) | GPTCR_CLKSOURCE_32 | GPTCR_FRR,
121 			&regs->gpt_tctl);
122 	writel(readl(&regs->gpt_tctl) | GPTCR_TEN, &regs->gpt_tctl);
123 
124 	return 0;
125 }
126 
127 unsigned long long get_ticks(void)
128 {
129 	struct gpt_regs *regs = (struct gpt_regs *)IMX_TIM1_BASE;
130 	ulong now = readl(&regs->gpt_tcn); /* current tick value */
131 
132 	if (now >= lastinc) {
133 		/*
134 		 * normal mode (non roll)
135 		 * move stamp forward with absolut diff ticks
136 		 */
137 		timestamp += (now - lastinc);
138 	} else {
139 		/* we have rollover of incrementer */
140 		timestamp += (0xFFFFFFFF - lastinc) + now;
141 	}
142 	lastinc = now;
143 	return timestamp;
144 }
145 
146 ulong get_timer_masked(void)
147 {
148 	/*
149 	 * get_ticks() returns a long long (64 bit), it wraps in
150 	 * 2^64 / CONFIG_MX27_CLK32 = 2^64 / 2^15 = 2^49 ~ 5 * 10^14 (s) ~
151 	 * 5 * 10^9 days... and get_ticks() * CONFIG_SYS_HZ wraps in
152 	 * 5 * 10^6 days - long enough.
153 	 */
154 	return tick_to_time(get_ticks());
155 }
156 
157 ulong get_timer(ulong base)
158 {
159 	return get_timer_masked() - base;
160 }
161 
162 /* delay x useconds AND preserve advance timstamp value */
163 void __udelay(unsigned long usec)
164 {
165 	unsigned long long tmp;
166 	ulong tmo;
167 
168 	tmo = us_to_tick(usec);
169 	tmp = get_ticks() + tmo;	/* get current timestamp */
170 
171 	while (get_ticks() < tmp)	/* loop till event */
172 		 /*NOP*/;
173 }
174 
175 ulong get_tbclk(void)
176 {
177 	return CONFIG_MX27_CLK32;
178 }
179