xref: /openbmc/u-boot/arch/arm/cpu/arm926ejs/mx27/reset.c (revision e11ef3d2)
1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3  * (C) Copyright 2002
4  * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
5  * Marius Groeger <mgroeger@sysgo.de>
6  *
7  * (C) Copyright 2002
8  * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
9  * Alex Zuepke <azu@sysgo.de>
10  *
11  * (C) Copyright 2002
12  * Gary Jennejohn, DENX Software Engineering, <gj@denx.de>
13  *
14  * (C) Copyright 2009
15  * Ilya Yanok, Emcraft Systems Ltd, <yanok@emcraft.com>
16  */
17 
18 #include <common.h>
19 #include <asm/io.h>
20 #include <asm/arch/imx-regs.h>
21 
22 /*
23  * Reset the cpu by setting up the watchdog timer and let it time out
24  */
25 void reset_cpu(ulong ignored)
26 {
27 	struct wdog_regs *regs = (struct wdog_regs *)IMX_WDT_BASE;
28 	/* Disable watchdog and set Time-Out field to 0 */
29 	writew(0x0000, &regs->wcr);
30 
31 	/* Write Service Sequence */
32 	writew(0x5555, &regs->wsr);
33 	writew(0xAAAA, &regs->wsr);
34 
35 	/* Enable watchdog */
36 	writew(WCR_WDE, &regs->wcr);
37 
38 	while (1);
39 	/*NOTREACHED*/
40 }
41