1 /* 2 * (C) Copyright 2009 DENX Software Engineering 3 * Author: John Rigby <jrigby@gmail.com> 4 * 5 * Based on mx27/generic.c: 6 * Copyright (c) 2008 Eric Jarrige <eric.jarrige@armadeus.org> 7 * Copyright (c) 2009 Ilya Yanok <yanok@emcraft.com> 8 * 9 * This program is free software; you can redistribute it and/or 10 * modify it under the terms of the GNU General Public License as 11 * published by the Free Software Foundation; either version 2 of 12 * the License, or (at your option) any later version. 13 * 14 * This program is distributed in the hope that it will be useful, 15 * but WITHOUT ANY WARRANTY; without even the implied warranty of 16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 17 * GNU General Public License for more details. 18 * 19 * You should have received a copy of the GNU General Public License 20 * along with this program; if not, write to the Free Software 21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 22 * MA 02111-1307 USA 23 */ 24 25 #include <common.h> 26 #include <div64.h> 27 #include <netdev.h> 28 #include <asm/io.h> 29 #include <asm/arch/imx-regs.h> 30 #include <asm/arch/imx25-pinmux.h> 31 #ifdef CONFIG_MXC_MMC 32 #include <asm/arch/mxcmmc.h> 33 #endif 34 35 /* 36 * get the system pll clock in Hz 37 * 38 * mfi + mfn / (mfd +1) 39 * f = 2 * f_ref * -------------------- 40 * pd + 1 41 */ 42 static unsigned int imx_decode_pll (unsigned int pll, unsigned int f_ref) 43 { 44 unsigned int mfi = (pll >> CCM_PLL_MFI_SHIFT) 45 & CCM_PLL_MFI_MASK; 46 unsigned int mfn = (pll >> CCM_PLL_MFN_SHIFT) 47 & CCM_PLL_MFN_MASK; 48 unsigned int mfd = (pll >> CCM_PLL_MFD_SHIFT) 49 & CCM_PLL_MFD_MASK; 50 unsigned int pd = (pll >> CCM_PLL_PD_SHIFT) 51 & CCM_PLL_PD_MASK; 52 53 mfi = mfi <= 5 ? 5 : mfi; 54 55 return lldiv (2 * (u64) f_ref * (mfi * (mfd + 1) + mfn), 56 (mfd + 1) * (pd + 1)); 57 } 58 59 static ulong imx_get_mpllclk (void) 60 { 61 struct ccm_regs *ccm = (struct ccm_regs *)IMX_CCM_BASE; 62 ulong fref = 24000000; 63 64 return imx_decode_pll (readl (&ccm->mpctl), fref); 65 } 66 67 ulong imx_get_armclk (void) 68 { 69 struct ccm_regs *ccm = (struct ccm_regs *)IMX_CCM_BASE; 70 ulong cctl = readl (&ccm->cctl); 71 ulong fref = imx_get_mpllclk (); 72 ulong div; 73 74 if (cctl & CCM_CCTL_ARM_SRC) 75 fref = lldiv ((fref * 3), 4); 76 77 div = ((cctl >> CCM_CCTL_ARM_DIV_SHIFT) 78 & CCM_CCTL_ARM_DIV_MASK) + 1; 79 80 return lldiv (fref, div); 81 } 82 83 ulong imx_get_ahbclk (void) 84 { 85 struct ccm_regs *ccm = (struct ccm_regs *)IMX_CCM_BASE; 86 ulong cctl = readl (&ccm->cctl); 87 ulong fref = imx_get_armclk (); 88 ulong div; 89 90 div = ((cctl >> CCM_CCTL_AHB_DIV_SHIFT) 91 & CCM_CCTL_AHB_DIV_MASK) + 1; 92 93 return lldiv (fref, div); 94 } 95 96 ulong imx_get_perclk (int clk) 97 { 98 struct ccm_regs *ccm = (struct ccm_regs *)IMX_CCM_BASE; 99 ulong fref = imx_get_ahbclk (); 100 ulong div; 101 102 div = readl (&ccm->pcdr[CCM_PERCLK_REG (clk)]); 103 div = ((div >> CCM_PERCLK_SHIFT (clk)) & CCM_PERCLK_MASK) + 1; 104 105 return lldiv (fref, div); 106 } 107 108 #if defined(CONFIG_DISPLAY_CPUINFO) 109 int print_cpuinfo (void) 110 { 111 char buf[32]; 112 113 printf ("CPU: Freescale i.MX25 at %s MHz\n\n", 114 strmhz (buf, imx_get_armclk ())); 115 return 0; 116 } 117 #endif 118 119 int cpu_eth_init (bd_t * bis) 120 { 121 #if defined(CONFIG_FEC_MXC) 122 struct ccm_regs *ccm = (struct ccm_regs *)IMX_CCM_BASE; 123 ulong val; 124 125 val = readl (&ccm->cgr0); 126 val |= (1 << 23); 127 writel (val, &ccm->cgr0); 128 return fecmxc_initialize (bis); 129 #else 130 return 0; 131 #endif 132 } 133 134 /* 135 * Initializes on-chip MMC controllers. 136 * to override, implement board_mmc_init() 137 */ 138 int cpu_mmc_init (bd_t * bis) 139 { 140 #ifdef CONFIG_MXC_MMC 141 return mxc_mmc_init (bis); 142 #else 143 return 0; 144 #endif 145 } 146 147 #ifdef CONFIG_MXC_UART 148 void mx25_uart1_init_pins(void) 149 { 150 struct iomuxc_mux_ctl *muxctl; 151 struct iomuxc_pad_ctl *padctl; 152 u32 inpadctl; 153 u32 outpadctl; 154 u32 muxmode0; 155 156 muxctl = (struct iomuxc_mux_ctl *)IMX_IOPADMUX_BASE; 157 padctl = (struct iomuxc_pad_ctl *)IMX_IOPADCTL_BASE; 158 muxmode0 = MX25_PIN_MUX_MODE (0); 159 /* 160 * set up input pins with hysteresis and 100K pull-ups 161 */ 162 inpadctl = MX25_PIN_PAD_CTL_HYS 163 | MX25_PIN_PAD_CTL_PKE 164 | MX25_PIN_PAD_CTL_PUE | MX25_PIN_PAD_CTL_100K_PU; 165 166 /* 167 * set up output pins with 100K pull-downs 168 * FIXME: need to revisit this 169 * PUE is ignored if PKE is not set 170 * so the right value here is likely 171 * 0x0 for no pull up/down 172 * or 173 * 0xc0 for 100k pull down 174 */ 175 outpadctl = MX25_PIN_PAD_CTL_PUE | MX25_PIN_PAD_CTL_100K_PD; 176 177 /* UART1 */ 178 /* rxd */ 179 writel (muxmode0, &muxctl->pad_uart1_rxd); 180 writel (inpadctl, &padctl->pad_uart1_rxd); 181 182 /* txd */ 183 writel (muxmode0, &muxctl->pad_uart1_txd); 184 writel (outpadctl, &padctl->pad_uart1_txd); 185 186 /* rts */ 187 writel (muxmode0, &muxctl->pad_uart1_rts); 188 writel (outpadctl, &padctl->pad_uart1_rts); 189 190 /* cts */ 191 writel (muxmode0, &muxctl->pad_uart1_cts); 192 writel (inpadctl, &padctl->pad_uart1_cts); 193 } 194 #endif /* CONFIG_MXC_UART */ 195 196 #ifdef CONFIG_FEC_MXC 197 void mx25_fec_init_pins (void) 198 { 199 struct iomuxc_mux_ctl *muxctl; 200 struct iomuxc_pad_ctl *padctl; 201 u32 inpadctl_100kpd; 202 u32 inpadctl_22kpu; 203 u32 outpadctl; 204 u32 muxmode0; 205 206 muxctl = (struct iomuxc_mux_ctl *)IMX_IOPADMUX_BASE; 207 padctl = (struct iomuxc_pad_ctl *)IMX_IOPADCTL_BASE; 208 muxmode0 = MX25_PIN_MUX_MODE (0); 209 inpadctl_100kpd = MX25_PIN_PAD_CTL_HYS 210 | MX25_PIN_PAD_CTL_PKE 211 | MX25_PIN_PAD_CTL_PUE | MX25_PIN_PAD_CTL_100K_PD; 212 inpadctl_22kpu = MX25_PIN_PAD_CTL_HYS 213 | MX25_PIN_PAD_CTL_PKE 214 | MX25_PIN_PAD_CTL_PUE | MX25_PIN_PAD_CTL_22K_PU; 215 /* 216 * set up output pins with 100K pull-downs 217 * FIXME: need to revisit this 218 * PUE is ignored if PKE is not set 219 * so the right value here is likely 220 * 0x0 for no pull 221 * or 222 * 0xc0 for 100k pull down 223 */ 224 outpadctl = MX25_PIN_PAD_CTL_PUE | MX25_PIN_PAD_CTL_100K_PD; 225 226 /* FEC_TX_CLK */ 227 writel (muxmode0, &muxctl->pad_fec_tx_clk); 228 writel (inpadctl_100kpd, &padctl->pad_fec_tx_clk); 229 230 /* FEC_RX_DV */ 231 writel (muxmode0, &muxctl->pad_fec_rx_dv); 232 writel (inpadctl_100kpd, &padctl->pad_fec_rx_dv); 233 234 /* FEC_RDATA0 */ 235 writel (muxmode0, &muxctl->pad_fec_rdata0); 236 writel (inpadctl_100kpd, &padctl->pad_fec_rdata0); 237 238 /* FEC_TDATA0 */ 239 writel (muxmode0, &muxctl->pad_fec_tdata0); 240 writel (outpadctl, &padctl->pad_fec_tdata0); 241 242 /* FEC_TX_EN */ 243 writel (muxmode0, &muxctl->pad_fec_tx_en); 244 writel (outpadctl, &padctl->pad_fec_tx_en); 245 246 /* FEC_MDC */ 247 writel (muxmode0, &muxctl->pad_fec_mdc); 248 writel (outpadctl, &padctl->pad_fec_mdc); 249 250 /* FEC_MDIO */ 251 writel (muxmode0, &muxctl->pad_fec_mdio); 252 writel (inpadctl_22kpu, &padctl->pad_fec_mdio); 253 254 /* FEC_RDATA1 */ 255 writel (muxmode0, &muxctl->pad_fec_rdata1); 256 writel (inpadctl_100kpd, &padctl->pad_fec_rdata1); 257 258 /* FEC_TDATA1 */ 259 writel (muxmode0, &muxctl->pad_fec_tdata1); 260 writel (outpadctl, &padctl->pad_fec_tdata1); 261 262 } 263 264 void imx_get_mac_from_fuse(unsigned char *mac) 265 { 266 int i; 267 struct iim_regs *iim = (struct iim_regs *)IMX_IIM_BASE; 268 struct fuse_bank *bank = &iim->bank[0]; 269 struct fuse_bank0_regs *fuse = 270 (struct fuse_bank0_regs *)bank->fuse_regs; 271 272 for (i = 0; i < 6; i++) 273 mac[i] = readl(&fuse->mac_addr[i]) & 0xff; 274 } 275 #endif /* CONFIG_FEC_MXC */ 276