1 /* 2 * (C) Copyright 2009 DENX Software Engineering 3 * Author: John Rigby <jrigby@gmail.com> 4 * 5 * Based on mx27/generic.c: 6 * Copyright (c) 2008 Eric Jarrige <eric.jarrige@armadeus.org> 7 * Copyright (c) 2009 Ilya Yanok <yanok@emcraft.com> 8 * 9 * This program is free software; you can redistribute it and/or 10 * modify it under the terms of the GNU General Public License as 11 * published by the Free Software Foundation; either version 2 of 12 * the License, or (at your option) any later version. 13 * 14 * This program is distributed in the hope that it will be useful, 15 * but WITHOUT ANY WARRANTY; without even the implied warranty of 16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 17 * GNU General Public License for more details. 18 * 19 * You should have received a copy of the GNU General Public License 20 * along with this program; if not, write to the Free Software 21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 22 * MA 02111-1307 USA 23 */ 24 25 #include <common.h> 26 #include <div64.h> 27 #include <netdev.h> 28 #include <asm/io.h> 29 #include <asm/arch/imx-regs.h> 30 #include <asm/arch/imx25-pinmux.h> 31 #ifdef CONFIG_MXC_MMC 32 #include <asm/arch/mxcmmc.h> 33 #endif 34 35 /* 36 * get the system pll clock in Hz 37 * 38 * mfi + mfn / (mfd +1) 39 * f = 2 * f_ref * -------------------- 40 * pd + 1 41 */ 42 static unsigned int imx_decode_pll(unsigned int pll, unsigned int f_ref) 43 { 44 unsigned int mfi = (pll >> CCM_PLL_MFI_SHIFT) 45 & CCM_PLL_MFI_MASK; 46 unsigned int mfn = (pll >> CCM_PLL_MFN_SHIFT) 47 & CCM_PLL_MFN_MASK; 48 unsigned int mfd = (pll >> CCM_PLL_MFD_SHIFT) 49 & CCM_PLL_MFD_MASK; 50 unsigned int pd = (pll >> CCM_PLL_PD_SHIFT) 51 & CCM_PLL_PD_MASK; 52 53 mfi = mfi <= 5 ? 5 : mfi; 54 55 return lldiv(2 * (u64) f_ref * (mfi * (mfd + 1) + mfn), 56 (mfd + 1) * (pd + 1)); 57 } 58 59 static ulong imx_get_mpllclk(void) 60 { 61 struct ccm_regs *ccm = (struct ccm_regs *)IMX_CCM_BASE; 62 ulong fref = 24000000; 63 64 return imx_decode_pll(readl(&ccm->mpctl), fref); 65 } 66 67 ulong imx_get_armclk(void) 68 { 69 struct ccm_regs *ccm = (struct ccm_regs *)IMX_CCM_BASE; 70 ulong cctl = readl(&ccm->cctl); 71 ulong fref = imx_get_mpllclk(); 72 ulong div; 73 74 if (cctl & CCM_CCTL_ARM_SRC) 75 fref = lldiv((fref * 3), 4); 76 77 div = ((cctl >> CCM_CCTL_ARM_DIV_SHIFT) 78 & CCM_CCTL_ARM_DIV_MASK) + 1; 79 80 return lldiv(fref, div); 81 } 82 83 ulong imx_get_ahbclk(void) 84 { 85 struct ccm_regs *ccm = (struct ccm_regs *)IMX_CCM_BASE; 86 ulong cctl = readl(&ccm->cctl); 87 ulong fref = imx_get_armclk(); 88 ulong div; 89 90 div = ((cctl >> CCM_CCTL_AHB_DIV_SHIFT) 91 & CCM_CCTL_AHB_DIV_MASK) + 1; 92 93 return lldiv(fref, div); 94 } 95 96 ulong imx_get_perclk(int clk) 97 { 98 struct ccm_regs *ccm = (struct ccm_regs *)IMX_CCM_BASE; 99 ulong fref = imx_get_ahbclk(); 100 ulong div; 101 102 div = readl(&ccm->pcdr[CCM_PERCLK_REG(clk)]); 103 div = ((div >> CCM_PERCLK_SHIFT(clk)) & CCM_PERCLK_MASK) + 1; 104 105 return lldiv(fref, div); 106 } 107 108 u32 get_cpu_rev(void) 109 { 110 u32 srev; 111 u32 system_rev = 0x25000; 112 113 /* read SREV register from IIM module */ 114 struct iim_regs *iim = (struct iim_regs *)IMX_IIM_BASE; 115 srev = readl(&iim->iim_srev); 116 117 switch (srev) { 118 case 0x00: 119 system_rev |= CHIP_REV_1_0; 120 break; 121 case 0x01: 122 system_rev |= CHIP_REV_1_1; 123 break; 124 default: 125 system_rev |= 0x8000; 126 break; 127 } 128 129 return system_rev; 130 } 131 132 #if defined(CONFIG_DISPLAY_CPUINFO) 133 static char *get_reset_cause(void) 134 { 135 /* read RCSR register from CCM module */ 136 struct ccm_regs *ccm = 137 (struct ccm_regs *)IMX_CCM_BASE; 138 139 u32 cause = readl(&ccm->rcsr) & 0x0f; 140 141 if (cause == 0) 142 return "POR"; 143 else if (cause == 1) 144 return "RST"; 145 else if ((cause & 2) == 2) 146 return "WDOG"; 147 else if ((cause & 4) == 4) 148 return "SW RESET"; 149 else if ((cause & 8) == 8) 150 return "JTAG"; 151 else 152 return "unknown reset"; 153 154 } 155 156 int print_cpuinfo(void) 157 { 158 char buf[32]; 159 u32 cpurev = get_cpu_rev(); 160 161 printf("CPU: Freescale i.MX25 rev%d.%d%s at %s MHz\n", 162 (cpurev & 0xF0) >> 4, (cpurev & 0x0F), 163 ((cpurev & 0x8000) ? " unknown" : ""), 164 strmhz(buf, imx_get_armclk())); 165 printf("Reset cause: %s\n\n", get_reset_cause()); 166 return 0; 167 } 168 #endif 169 170 int cpu_eth_init(bd_t *bis) 171 { 172 #if defined(CONFIG_FEC_MXC) 173 struct ccm_regs *ccm = (struct ccm_regs *)IMX_CCM_BASE; 174 ulong val; 175 176 val = readl(&ccm->cgr0); 177 val |= (1 << 23); 178 writel(val, &ccm->cgr0); 179 return fecmxc_initialize(bis); 180 #else 181 return 0; 182 #endif 183 } 184 185 /* 186 * Initializes on-chip MMC controllers. 187 * to override, implement board_mmc_init() 188 */ 189 int cpu_mmc_init(bd_t *bis) 190 { 191 #ifdef CONFIG_MXC_MMC 192 return mxc_mmc_init(bis); 193 #else 194 return 0; 195 #endif 196 } 197 198 #ifdef CONFIG_MXC_UART 199 void mx25_uart1_init_pins(void) 200 { 201 struct iomuxc_mux_ctl *muxctl; 202 struct iomuxc_pad_ctl *padctl; 203 u32 inpadctl; 204 u32 outpadctl; 205 u32 muxmode0; 206 207 muxctl = (struct iomuxc_mux_ctl *)IMX_IOPADMUX_BASE; 208 padctl = (struct iomuxc_pad_ctl *)IMX_IOPADCTL_BASE; 209 muxmode0 = MX25_PIN_MUX_MODE(0); 210 /* 211 * set up input pins with hysteresis and 100K pull-ups 212 */ 213 inpadctl = MX25_PIN_PAD_CTL_HYS 214 | MX25_PIN_PAD_CTL_PKE 215 | MX25_PIN_PAD_CTL_PUE | MX25_PIN_PAD_CTL_100K_PU; 216 217 /* 218 * set up output pins with 100K pull-downs 219 * FIXME: need to revisit this 220 * PUE is ignored if PKE is not set 221 * so the right value here is likely 222 * 0x0 for no pull up/down 223 * or 224 * 0xc0 for 100k pull down 225 */ 226 outpadctl = MX25_PIN_PAD_CTL_PUE | MX25_PIN_PAD_CTL_100K_PD; 227 228 /* UART1 */ 229 /* rxd */ 230 writel(muxmode0, &muxctl->pad_uart1_rxd); 231 writel(inpadctl, &padctl->pad_uart1_rxd); 232 233 /* txd */ 234 writel(muxmode0, &muxctl->pad_uart1_txd); 235 writel(outpadctl, &padctl->pad_uart1_txd); 236 237 /* rts */ 238 writel(muxmode0, &muxctl->pad_uart1_rts); 239 writel(outpadctl, &padctl->pad_uart1_rts); 240 241 /* cts */ 242 writel(muxmode0, &muxctl->pad_uart1_cts); 243 writel(inpadctl, &padctl->pad_uart1_cts); 244 } 245 #endif /* CONFIG_MXC_UART */ 246 247 #ifdef CONFIG_FEC_MXC 248 void mx25_fec_init_pins(void) 249 { 250 struct iomuxc_mux_ctl *muxctl; 251 struct iomuxc_pad_ctl *padctl; 252 u32 inpadctl_100kpd; 253 u32 inpadctl_22kpu; 254 u32 outpadctl; 255 u32 muxmode0; 256 257 muxctl = (struct iomuxc_mux_ctl *)IMX_IOPADMUX_BASE; 258 padctl = (struct iomuxc_pad_ctl *)IMX_IOPADCTL_BASE; 259 muxmode0 = MX25_PIN_MUX_MODE(0); 260 inpadctl_100kpd = MX25_PIN_PAD_CTL_HYS 261 | MX25_PIN_PAD_CTL_PKE 262 | MX25_PIN_PAD_CTL_PUE | MX25_PIN_PAD_CTL_100K_PD; 263 inpadctl_22kpu = MX25_PIN_PAD_CTL_HYS 264 | MX25_PIN_PAD_CTL_PKE 265 | MX25_PIN_PAD_CTL_PUE | MX25_PIN_PAD_CTL_22K_PU; 266 /* 267 * set up output pins with 100K pull-downs 268 * FIXME: need to revisit this 269 * PUE is ignored if PKE is not set 270 * so the right value here is likely 271 * 0x0 for no pull 272 * or 273 * 0xc0 for 100k pull down 274 */ 275 outpadctl = MX25_PIN_PAD_CTL_PUE | MX25_PIN_PAD_CTL_100K_PD; 276 277 /* FEC_TX_CLK */ 278 writel(muxmode0, &muxctl->pad_fec_tx_clk); 279 writel(inpadctl_100kpd, &padctl->pad_fec_tx_clk); 280 281 /* FEC_RX_DV */ 282 writel(muxmode0, &muxctl->pad_fec_rx_dv); 283 writel(inpadctl_100kpd, &padctl->pad_fec_rx_dv); 284 285 /* FEC_RDATA0 */ 286 writel(muxmode0, &muxctl->pad_fec_rdata0); 287 writel(inpadctl_100kpd, &padctl->pad_fec_rdata0); 288 289 /* FEC_TDATA0 */ 290 writel(muxmode0, &muxctl->pad_fec_tdata0); 291 writel(outpadctl, &padctl->pad_fec_tdata0); 292 293 /* FEC_TX_EN */ 294 writel(muxmode0, &muxctl->pad_fec_tx_en); 295 writel(outpadctl, &padctl->pad_fec_tx_en); 296 297 /* FEC_MDC */ 298 writel(muxmode0, &muxctl->pad_fec_mdc); 299 writel(outpadctl, &padctl->pad_fec_mdc); 300 301 /* FEC_MDIO */ 302 writel(muxmode0, &muxctl->pad_fec_mdio); 303 writel(inpadctl_22kpu, &padctl->pad_fec_mdio); 304 305 /* FEC_RDATA1 */ 306 writel(muxmode0, &muxctl->pad_fec_rdata1); 307 writel(inpadctl_100kpd, &padctl->pad_fec_rdata1); 308 309 /* FEC_TDATA1 */ 310 writel(muxmode0, &muxctl->pad_fec_tdata1); 311 writel(outpadctl, &padctl->pad_fec_tdata1); 312 313 } 314 315 void imx_get_mac_from_fuse(unsigned char *mac) 316 { 317 int i; 318 struct iim_regs *iim = (struct iim_regs *)IMX_IIM_BASE; 319 struct fuse_bank *bank = &iim->bank[0]; 320 struct fuse_bank0_regs *fuse = 321 (struct fuse_bank0_regs *)bank->fuse_regs; 322 323 for (i = 0; i < 6; i++) 324 mac[i] = readl(&fuse->mac_addr[i]) & 0xff; 325 } 326 #endif /* CONFIG_FEC_MXC */ 327