1 /*
2  * (C) Copyright 2009 DENX Software Engineering
3  * Author: John Rigby <jrigby@gmail.com>
4  *
5  * Based on mx27/generic.c:
6  *  Copyright (c) 2008 Eric Jarrige <eric.jarrige@armadeus.org>
7  *  Copyright (c) 2009 Ilya Yanok <yanok@emcraft.com>
8  *
9  * SPDX-License-Identifier:	GPL-2.0+
10  */
11 
12 #include <common.h>
13 #include <div64.h>
14 #include <netdev.h>
15 #include <asm/io.h>
16 #include <asm/arch/imx-regs.h>
17 #include <asm/arch/clock.h>
18 
19 #ifdef CONFIG_FSL_ESDHC
20 #include <fsl_esdhc.h>
21 
22 DECLARE_GLOBAL_DATA_PTR;
23 #endif
24 
25 /*
26  *  get the system pll clock in Hz
27  *
28  *                  mfi + mfn / (mfd +1)
29  *  f = 2 * f_ref * --------------------
30  *                        pd + 1
31  */
32 static unsigned int imx_decode_pll(unsigned int pll, unsigned int f_ref)
33 {
34 	unsigned int mfi = (pll >> CCM_PLL_MFI_SHIFT)
35 	    & CCM_PLL_MFI_MASK;
36 	int mfn = (pll >> CCM_PLL_MFN_SHIFT)
37 	    & CCM_PLL_MFN_MASK;
38 	unsigned int mfd = (pll >> CCM_PLL_MFD_SHIFT)
39 	    & CCM_PLL_MFD_MASK;
40 	unsigned int pd = (pll >> CCM_PLL_PD_SHIFT)
41 	    & CCM_PLL_PD_MASK;
42 
43 	mfi = mfi <= 5 ? 5 : mfi;
44 	mfn = mfn >= 512 ? mfn - 1024 : mfn;
45 	mfd += 1;
46 	pd += 1;
47 
48 	return lldiv(2 * (u64) f_ref * (mfi * mfd + mfn),
49 		     mfd * pd);
50 }
51 
52 static ulong imx_get_mpllclk(void)
53 {
54 	struct ccm_regs *ccm = (struct ccm_regs *)IMX_CCM_BASE;
55 	ulong fref = MXC_HCLK;
56 
57 	return imx_decode_pll(readl(&ccm->mpctl), fref);
58 }
59 
60 static ulong imx_get_armclk(void)
61 {
62 	struct ccm_regs *ccm = (struct ccm_regs *)IMX_CCM_BASE;
63 	ulong cctl = readl(&ccm->cctl);
64 	ulong fref = imx_get_mpllclk();
65 	ulong div;
66 
67 	if (cctl & CCM_CCTL_ARM_SRC)
68 		fref = lldiv((u64) fref * 3, 4);
69 
70 	div = ((cctl >> CCM_CCTL_ARM_DIV_SHIFT)
71 	       & CCM_CCTL_ARM_DIV_MASK) + 1;
72 
73 	return fref / div;
74 }
75 
76 static ulong imx_get_ahbclk(void)
77 {
78 	struct ccm_regs *ccm = (struct ccm_regs *)IMX_CCM_BASE;
79 	ulong cctl = readl(&ccm->cctl);
80 	ulong fref = imx_get_armclk();
81 	ulong div;
82 
83 	div = ((cctl >> CCM_CCTL_AHB_DIV_SHIFT)
84 	       & CCM_CCTL_AHB_DIV_MASK) + 1;
85 
86 	return fref / div;
87 }
88 
89 static ulong imx_get_ipgclk(void)
90 {
91 	return imx_get_ahbclk() / 2;
92 }
93 
94 static ulong imx_get_perclk(int clk)
95 {
96 	struct ccm_regs *ccm = (struct ccm_regs *)IMX_CCM_BASE;
97 	ulong fref = imx_get_ahbclk();
98 	ulong div;
99 
100 	div = readl(&ccm->pcdr[CCM_PERCLK_REG(clk)]);
101 	div = ((div >> CCM_PERCLK_SHIFT(clk)) & CCM_PERCLK_MASK) + 1;
102 
103 	return fref / div;
104 }
105 
106 unsigned int mxc_get_clock(enum mxc_clock clk)
107 {
108 	if (clk >= MXC_CLK_NUM)
109 		return -1;
110 	switch (clk) {
111 	case MXC_ARM_CLK:
112 		return imx_get_armclk();
113 	case MXC_AHB_CLK:
114 		return imx_get_ahbclk();
115 	case MXC_IPG_CLK:
116 	case MXC_CSPI_CLK:
117 	case MXC_FEC_CLK:
118 		return imx_get_ipgclk();
119 	default:
120 		return imx_get_perclk(clk);
121 	}
122 }
123 
124 u32 get_cpu_rev(void)
125 {
126 	u32 srev;
127 	u32 system_rev = 0x25000;
128 
129 	/* read SREV register from IIM module */
130 	struct iim_regs *iim = (struct iim_regs *)IMX_IIM_BASE;
131 	srev = readl(&iim->iim_srev);
132 
133 	switch (srev) {
134 	case 0x00:
135 		system_rev |= CHIP_REV_1_0;
136 		break;
137 	case 0x01:
138 		system_rev |= CHIP_REV_1_1;
139 		break;
140 	case 0x02:
141 		system_rev |= CHIP_REV_1_2;
142 		break;
143 	default:
144 		system_rev |= 0x8000;
145 		break;
146 	}
147 
148 	return system_rev;
149 }
150 
151 #if defined(CONFIG_DISPLAY_CPUINFO)
152 static char *get_reset_cause(void)
153 {
154 	/* read RCSR register from CCM module */
155 	struct ccm_regs *ccm =
156 		(struct ccm_regs *)IMX_CCM_BASE;
157 
158 	u32 cause = readl(&ccm->rcsr) & 0x0f;
159 
160 	if (cause == 0)
161 		return "POR";
162 	else if (cause == 1)
163 		return "RST";
164 	else if ((cause & 2) == 2)
165 		return "WDOG";
166 	else if ((cause & 4) == 4)
167 		return "SW RESET";
168 	else if ((cause & 8) == 8)
169 		return "JTAG";
170 	else
171 		return "unknown reset";
172 
173 }
174 
175 int print_cpuinfo(void)
176 {
177 	char buf[32];
178 	u32 cpurev = get_cpu_rev();
179 
180 	printf("CPU:   Freescale i.MX25 rev%d.%d%s at %s MHz\n",
181 		(cpurev & 0xF0) >> 4, (cpurev & 0x0F),
182 		((cpurev & 0x8000) ? " unknown" : ""),
183 		strmhz(buf, imx_get_armclk()));
184 	printf("Reset cause: %s\n\n", get_reset_cause());
185 	return 0;
186 }
187 #endif
188 
189 void enable_caches(void)
190 {
191 #ifndef CONFIG_SYS_DCACHE_OFF
192 	/* Enable D-cache. I-cache is already enabled in start.S */
193 	dcache_enable();
194 #endif
195 }
196 
197 #if defined(CONFIG_FEC_MXC)
198 /*
199  * Initializes on-chip ethernet controllers.
200  * to override, implement board_eth_init()
201  */
202 int cpu_eth_init(bd_t *bis)
203 {
204 	struct ccm_regs *ccm = (struct ccm_regs *)IMX_CCM_BASE;
205 	ulong val;
206 
207 	val = readl(&ccm->cgr0);
208 	val |= (1 << 23);
209 	writel(val, &ccm->cgr0);
210 	return fecmxc_initialize(bis);
211 }
212 #endif
213 
214 int get_clocks(void)
215 {
216 #ifdef CONFIG_FSL_ESDHC
217 #if CONFIG_SYS_FSL_ESDHC_ADDR == IMX_MMC_SDHC2_BASE
218 	gd->arch.sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK);
219 #else
220 	gd->arch.sdhc_clk = mxc_get_clock(MXC_ESDHC1_CLK);
221 #endif
222 #endif
223 	return 0;
224 }
225 
226 #ifdef CONFIG_FSL_ESDHC
227 /*
228  * Initializes on-chip MMC controllers.
229  * to override, implement board_mmc_init()
230  */
231 int cpu_mmc_init(bd_t *bis)
232 {
233 	return fsl_esdhc_mmc_init(bis);
234 }
235 #endif
236 
237 #ifdef CONFIG_FEC_MXC
238 void imx_get_mac_from_fuse(int dev_id, unsigned char *mac)
239 {
240 	int i;
241 	struct iim_regs *iim = (struct iim_regs *)IMX_IIM_BASE;
242 	struct fuse_bank *bank = &iim->bank[0];
243 	struct fuse_bank0_regs *fuse =
244 			(struct fuse_bank0_regs *)bank->fuse_regs;
245 
246 	for (i = 0; i < 6; i++)
247 		mac[i] = readl(&fuse->mac_addr[i]) & 0xff;
248 }
249 #endif /* CONFIG_FEC_MXC */
250