1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3  * LPC32xx dram init
4  *
5  * (C) Copyright 2014  DENX Software Engineering GmbH
6  * Written-by: Albert ARIBAUD <albert.aribaud@3adev.fr>
7  *
8  * This is called by SPL to gain access to the SDR DRAM.
9  *
10  * This code runs from SRAM.
11  */
12 
13 #include <common.h>
14 #include <netdev.h>
15 #include <asm/arch/cpu.h>
16 #include <asm/arch/clk.h>
17 #include <asm/arch/wdt.h>
18 #include <asm/arch/emc.h>
19 #include <asm/io.h>
20 
21 static struct clk_pm_regs *clk = (struct clk_pm_regs *)CLK_PM_BASE;
22 static struct emc_regs *emc = (struct emc_regs *)EMC_BASE;
23 
24 void ddr_init(struct emc_dram_settings *dram)
25 {
26 	uint32_t ck;
27 
28 	/* Enable EMC interface and choose little endian mode */
29 	writel(1, &emc->ctrl);
30 	writel(0, &emc->config);
31 	/* Select maximum EMC Dynamic Memory Refresh Time */
32 	writel(0x7FF, &emc->refresh);
33 	/* Determine CLK */
34 	ck = get_sdram_clk_rate();
35 	/* Configure SDRAM */
36 	writel(dram->cmddelay, &clk->sdramclk_ctrl);
37 	writel(dram->config0, &emc->config0);
38 	writel(dram->rascas0, &emc->rascas0);
39 	writel(dram->rdconfig, &emc->read_config);
40 	/* Set timings */
41 	writel((ck / dram->trp) & 0x0000000F, &emc->t_rp);
42 	writel((ck / dram->tras) & 0x0000000F, &emc->t_ras);
43 	writel((ck / dram->tsrex) & 0x0000007F, &emc->t_srex);
44 	writel((ck / dram->twr) & 0x0000000F, &emc->t_wr);
45 	writel((ck / dram->trc) & 0x0000001F, &emc->t_rc);
46 	writel((ck / dram->trfc) & 0x0000001F, &emc->t_rfc);
47 	writel((ck / dram->txsr) & 0x000000FF, &emc->t_xsr);
48 	writel(dram->trrd, &emc->t_rrd);
49 	writel(dram->tmrd, &emc->t_mrd);
50 	writel(dram->tcdlr, &emc->t_cdlr);
51 	/* Dynamic refresh */
52 	writel((((ck / dram->refresh) >> 4) & 0x7FF), &emc->refresh);
53 	udelay(10);
54 	/* Force all clocks, enable inverted ck, issue NOP command */
55 	writel(0x00000193, &emc->control);
56 	udelay(100);
57 	/* Keep all clocks enabled, issue a PRECHARGE ALL command */
58 	writel(0x00000113, &emc->control);
59 	/* Fast dynamic refresh for at least a few SDRAM ck cycles */
60 	writel((((128) >> 4) & 0x7FF), &emc->refresh);
61 	udelay(10);
62 	/* set correct dynamic refresh timing */
63 	writel((((ck / dram->refresh) >> 4) & 0x7FF), &emc->refresh);
64 	udelay(10);
65 	/* set normal mode to CAS=3 */
66 	writel(0x00000093, &emc->control);
67 	readl(EMC_DYCS0_BASE | dram->mode);
68 	/* set extended mode to all zeroes */
69 	writel(0x00000093, &emc->control);
70 	readl(EMC_DYCS0_BASE | dram->emode);
71 	/* stop forcing clocks, keep inverted clock, issue normal mode */
72 	writel(0x00000010, &emc->control);
73 }
74