1 /*
2  * Copyright (C) 2011 by Vladimir Zapolskiy <vz@mleia.com>
3  *
4  * SPDX-License-Identifier:	GPL-2.0+
5  */
6 
7 #include <common.h>
8 #include <asm/arch/cpu.h>
9 #include <asm/arch/clk.h>
10 #include <asm/arch/uart.h>
11 #include <asm/arch/mux.h>
12 #include <asm/io.h>
13 #include <dm.h>
14 
15 static struct clk_pm_regs    *clk  = (struct clk_pm_regs *)CLK_PM_BASE;
16 static struct uart_ctrl_regs *ctrl = (struct uart_ctrl_regs *)UART_CTRL_BASE;
17 static struct mux_regs *mux = (struct mux_regs *)MUX_BASE;
18 
19 void lpc32xx_uart_init(unsigned int uart_id)
20 {
21 	if (uart_id < 1 || uart_id > 7)
22 		return;
23 
24 	/* Disable loopback mode, if it is set by S1L bootloader */
25 	clrbits_le32(&ctrl->loop,
26 		     UART_LOOPBACK(CONFIG_SYS_LPC32XX_UART));
27 
28 	if (uart_id < 3 || uart_id > 6)
29 		return;
30 
31 	/* Enable UART system clock */
32 	setbits_le32(&clk->uartclk_ctrl, CLK_UART(uart_id));
33 
34 	/* Set UART into autoclock mode */
35 	clrsetbits_le32(&ctrl->clkmode,
36 			UART_CLKMODE_MASK(uart_id),
37 			UART_CLKMODE_AUTO(uart_id));
38 
39 	/* Bypass pre-divider of UART clock */
40 	writel(CLK_UART_X_DIV(1) | CLK_UART_Y_DIV(1),
41 	       &clk->u3clk + (uart_id - 3));
42 }
43 
44 void lpc32xx_mac_init(void)
45 {
46 	/* Enable MAC interface */
47 	writel(CLK_MAC_REG | CLK_MAC_SLAVE | CLK_MAC_MASTER
48 		| CLK_MAC_MII, &clk->macclk_ctrl);
49 }
50 
51 void lpc32xx_mlc_nand_init(void)
52 {
53 	/* Enable NAND interface */
54 	writel(CLK_NAND_MLC | CLK_NAND_MLC_INT, &clk->flashclk_ctrl);
55 }
56 
57 void lpc32xx_i2c_init(unsigned int devnum)
58 {
59 	/* Enable I2C interface */
60 	uint32_t ctrl = readl(&clk->i2cclk_ctrl);
61 	if (devnum == 1)
62 		ctrl |= CLK_I2C1_ENABLE;
63 	if (devnum == 2)
64 		ctrl |= CLK_I2C2_ENABLE;
65 	writel(ctrl, &clk->i2cclk_ctrl);
66 }
67 
68 U_BOOT_DEVICE(lpc32xx_gpios) = {
69 	.name = "gpio_lpc32xx"
70 };
71 
72 /* Mux for SCK0, MISO0, MOSI0. We do not use SSEL0. */
73 
74 #define P_MUX_SET_SSP0 0x1600
75 
76 void lpc32xx_ssp_init(void)
77 {
78 	/* Enable SSP0 interface */
79 	writel(CLK_SSP0_ENABLE_CLOCK, &clk->ssp_ctrl);
80 	/* Mux SSP0 pins */
81 	writel(P_MUX_SET_SSP0, &mux->p_mux_set);
82 }
83